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SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter (DUART)
Rev. 07 -- 19 December 2007 Product data sheet
1. General description
The SC28L92 is a pin and function replacement for the SCC2692 and SC26C92 operating at 3.3 V or 5 V supply with added features and deeper FIFOs. Its configuration on power-up is that of the SC26C92. Its differences from the SCC2692 and SC26C92 are: 16 character receiver, 16 character transmit FIFOs, watchdog timer for each receiver, mode register 0 is added, extended baud rate and overall faster speeds, programmable receiver and transmitter interrupts. (Neither the SC26C92 nor the SCC2692 is being discontinued.) Pin programming will allow the device to operate with either the Motorola or Intel bus interface. The bit 3 of the MR0A register allows the device to operate in an 8 byte FIFO mode if strict compliance with the SC26C92 FIFO structure is required. The NXP Semiconductors SC28L92 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip CMOS-LSI communications device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt driven system with modem and DMA interface. The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of 28 fixed baud rates; a 16x clock derived from a programmable counter/timer, or an external 1x or 16x clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems. Each receiver and transmitter is buffered by 8 or 16 character FIFOs to minimize the potential of receiver overrun, transmitter underrun and to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability is provided via RTS/CTS signaling to disable a remote transmitter when the receiver buffer is full. Also provided on the SC28L92 are a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control. The SC28L92 is available in three package versions: PLCC44, QFP44, and HVQFN48.
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
2. Features
I Member of IMPACT family: 3.3 V to 5.0 V, -40 C to +85 C and 68xxx or 80xxx bus interface for all devices I Dual full-duplex independent asynchronous receiver/transmitters I 16 character FIFOs for each receiver and transmitter I Pin programming selects 68xxx or 80xxx bus interface I Programmable data format N 5 data to 8 data bits plus parity N Odd, even, no parity or force parity N 1 stop, 1.5 stop or 2 stop bits programmable in 116-bit increments I 16-bit programmable counter/timer I Programmable baud rate for each receiver and transmitter selectable from: N 28 fixed rates: 50 kBd to 230.4 kBd N Other baud rates to 1 MHz at 16x N Programmable user-defined rates derived from a programmable counter/timer N External 1x or 16x clock I Parity, framing, and overrun error detection I False start bit detection I Line break detection and generation I Programmable channel mode N Normal (full-duplex) N Automatic echo N Local loopback N Remote loopback N Multi-drop mode (also called wake-up or 9-bit) I Multi-function 7-bit input port (includes IACKN) N Can serve as clock or control inputs N Change of state detection on four inputs N Inputs have typically > 100 k pull-up resistors N Change of state detectors for modem control I Multi-function 8-bit output port N Individual bit set/reset capability N Outputs can be programmed to be status/interrupt signals N FIFO status for DMA interface I Versatile interrupt system N Single interrupt output with eight maskable interrupting conditions N Output port can be configured to provide a total of up to six separate interrupt outputs that may be wire ORed N Each FIFO can be programmed for four different interrupt levels N Watchdog timer for each receiver I Maximum data transfer rates: 1x - 1 Mbit/s, 16x - 1 Mbit/s I Automatic wake-up mode for multi-drop applications I Start-end break interrupt/status I Detects break which originates in the middle of a character
SC28L92_7 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 -- 19 December 2007
2 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
I I I I I
On-chip crystal oscillator Power-down mode Receiver time-out mode Single 3.3 V or 5 V power supply Powers up to emulate SC26C92
3. Ordering information
Table 1. Ordering information VCC = 3.3 V 10 % or VCC = 5.0 V 10 %; Tamb = -40 C to +85 C Type number SC28L92A1A SC28L92A1B SC28L92A1BS Package Name PLCC44 QFP44 HVQFN48 Description plastic leaded chip carrier; 44 leads plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 6 x 6 x 0.85 mm Version SOT187-2 SOT307-2 SOT778-4
SC28L92_7
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 -- 19 December 2007
3 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
4. Block diagram
SC28L92 (80xxx mode)
8
D0 to D7
BUS BUFFER
CHANNEL A 16-BYTE TRANSMIT FIFO TxDA
RDN WRN CEN A0 to A3 RESET I/M open or connect to VCC for 80xxx
4
OPERATION CONTROL ADDRESS DECODE R/W CONTROL
TRANSMIT SHIFT REGISTER 16-BYTE RECEIVE FIFO WATCHDOG TIMER RECEIVE SHIFT REGISTER RxDA
INTERRUPT CONTROL IMR ISR INTERNAL DATA BUS GP
MRA0, 1, 2, 3 CRA SRA
INTRN
TxDB CHANNEL B (AS ABOVE) RxDB
control
timing
INPUT PORT CHANGE-OFSTATE DETECTORS (4)
TIMING BAUD RATE GENERATOR CLOCK SELECTORS COUNTER/ TIMER XTAL OSCILLATOR CSRA CSRB ACR CTL CTU
7
IP0 to IP6
IPCR ACR
X1/CLK X2
OUTPUT PORT FUNCTION SELECT LOGIC OPCR OPR
8
OP0 to OP7
002aad459
The data pins TxD and RxD are considered idle at the logic 1 (HIGH) level when inactive, or active when at the logic 0 (LOW) level. Comments about these levels when RS232 is referenced often refer to Mark and Space levels. Mark usually means inactive and Space means active. The voltage levels represented by the terms Mark and Space are often reversed from those above: Mark is low voltage, and Space is high voltage.
Fig 1. Block diagram (80xxx mode)
SC28L92_7
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Product data sheet
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4 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
SC28L92 (68xxx mode)
8
D0 to D7
BUS BUFFER
CHANNEL A 16-BYTE TRANSMIT FIFO TxDA
R/WN IACKN CEN A0 to A3 RESETN I/M ground for 68xxx mode
4
OPERATION CONTROL ADDRESS DECODE R/W CONTROL
TRANSMIT SHIFT REGISTER 16-BYTE RECEIVE FIFO WATCHDOG TIMER RECEIVE SHIFT REGISTER RxDA
INTERRUPT CONTROL IMR ISR INTERNAL DATA BUS
MRA0, 1, 2, 3 CRA SRA
INTRN DACKN
GP
TxDB CHANNEL B (AS ABOVE) RxDB
control timing
INPUT PORT CHANGE-OFSTATE DETECTORS (4)
TIMING BAUD RATE GENERATOR CLOCK SELECTORS COUNTER/ TIMER XTAL OSCILLATOR CSRA CSRB ACR CTL CTU
6
IP0 to IP5
IPCR ACR
X1/CLK X2
OUTPUT PORT FUNCTION SELECT LOGIC OPCR OPR
8
OP0 to OP7
002aad460
The data pins TxD and RxD are considered idle at the logic 1 (HIGH) level when inactive, or active when at the logic 0 (LOW) level. Comments about these levels when RS232 is referenced often refer to Mark and Space levels. Mark usually means inactive and Space means active. The voltage levels represented by the terms Mark and Space are often reversed from those above: Mark is low voltage, and Space is high voltage.
Fig 2. Block diagram (68xxx mode)
SC28L92_7
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 -- 19 December 2007
5 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
5. Pinning information
5.1 Pinning
44 VCC IP1 IP3 n.c. 43 IP4 42 IP5 41 IP6 40 IP2 39 CEN 38 RESET 37 X2 36 X1/CLK 35 RxDA 34 n.c. 33 TxDA 32 OP0 31 OP2 30 OP4 29 OP6 D1 18 D3 19 D5 20 D7 21 GND 22 n.c. 23 INTRN 24 D6 25 D4 26 D2 27 D0 28 40 IP2 39 CEN 38 RESETN 37 X2 36 X1/CLK 35 RxDA 34 n.c. 33 TxDA 32 OP0 31 OP2 30 OP4 29 OP6 D1 18 D3 19 D5 20 D7 21 GND 22 n.c. 23 INTRN 24 D6 25 D4 26 D2 27 D0 28
002aad413 002aad412
A2
A1
6
5
4
3
2
A0
A3 IP0 WRN
7 8 9
RDN 10 RxDB 11 I/M 12 TxDB 13 OP1 14 OP3 15 OP5 16 OP7 17
SC28L92A1A
(80xxx mode)
Fig 3. Pin configuration for PLCC44; 80xxx mode
41 IACKN
1 n.c.
44 VCC
IP1
IP3
43 IP4
A3 IP0 R/WN
7 8 9
DACKN 10 RxDB 11 I/M 12 TxDB 13 OP1 14 OP3 15 OP5 16 OP7 17
SC28L92A1A
(68xxx mode)
Fig 4. Pin configuration for PLCC44; 68xxx mode
SC28L92_7
42 IP5
A2
A1
6
5
4
3
2
A0
1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 -- 19 December 2007
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NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
39 VCC
38 VCC
43 IP1
41 IP3
37 IP4
36 IP5
35 IP6
A3 IP0 WRN RDN RxDB TxDB OP1 OP3 OP5
1 2 3 4 5 6 7 8 9
34 IP2 33 CEN 32 RESET 31 X2 30 X1/CLK 29 RxDA 28 TxDA 27 OP0 26 OP2 25 OP4 24 OP6 23 n.c. D0 22 34 IP2 33 CEN 32 RESETN 31 X2 30 X1/CLK 29 RxDA 28 TxDA 27 OP0 26 OP2 25 OP4 24 OP6 23 n.c. D0 22
002aad415 002aad414
44 A2
42 A1 D5 14
SC28L92A1B
(80xxx mode)
OP7 10 I/M 11 D1 12 D3 13 D7 15 GND 16 GND 17 INTRN 18 D6 19 D4 20 D4 20 36 IP5 D2 21 D2 21 35 IACKN
Fig 5. Pin configuration for QFP44; 80xxx mode
40 A0
39 VCC GND 17
38 VCC INTRN 18
43 IP1
41 IP3
A3 IP0 R/WN DACKN RxDB TxDB OP1 OP3 OP5
1 2 3 4 5 6 7 8 9
SC28L92A1B
(68xxx mode)
OP7 10 I/M 11 D1 12 D3 13 D5 14 D7 15 GND 16 D6 19
Fig 6. Pin configuration for QFP44; 68xxx mode
SC28L92_7
37 IP4
44 A2
42 A1
40 A0
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Product data sheet
Rev. 07 -- 19 December 2007
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NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
42 VCC
43 n.c.
48 A2
46 A1
A3 IP0 WRN RDN RxDB n.c. I/M TxDB OP1
1 2 3 4 5 6 7 8 9
44 A0
terminal 1 index area
37 n.c. 36 n.c. 35 CEN 34 RESET 33 X2 32 X1/CLK 31 RxDA 30 TxDA 29 OP0 28 OP2 27 OP4 26 OP6 25 n.c. n.c. 24 37 n.c. 36 n.c. 35 CEN 34 RESETN 33 X2 32 X1/CLK 31 RxDA 30 TxDA 29 OP0 28 OP2 27 OP4 26 OP6 25 n.c. n.c. 24
002aad363 002aad362
47 IP1
45 IP3
41 IP4
40 IP5 D4 21 40 IP5 D4 21
39 IP6 D2 22 39 IACKN D2 22
SC28L92A1BS
(80xxx mode)
OP3 10 OP5 11 OP7 12 n.c. 13 D1 14 D3 15 D5 16 D7 17 GND 18 INTRN 19 D6 20 D0 23 D0 23 38 IP2
Transparent top view
Fig 7. Pin configuration for HVQFN48; 80xxx mode
48 A2
46 A1
A3 IP0 R/WN DACKN RxDB n.c. I/M TxDB OP1
1 2 3 4 5 6 7 8 9
SC28L92A1BS
(68xxx mode)
OP3 10 OP5 11 OP7 12 n.c. 13 D1 14 D3 15 D5 16 D7 17 GND 18 INTRN 19 D6 20
Transparent top view
Fig 8. Pin configuration for HVQFN48; 68xxx mode
SC28L92_7
44 A0
terminal 1 index area
42 VCC 41 IP4
43 n.c.
47 IP1
45 IP3
38 IP2
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Product data sheet
Rev. 07 -- 19 December 2007
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NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
5.2 Pin description
Table 2. Symbol I/M D0 D1 D2 D3 D4 D5 D6 D7 CEN Pin description for 80xxx bus interface (Intel) Pin PLCC44 QFP44 HVQFN48 12 28 18 27 19 26 20 25 21 39 11 22 12 21 13 20 14 19 15 33 7 23 14 22 15 21 16 20 17 35 I I/O I/O I/O I/O I/O I/O I/O I/O I Chip enable: Active LOW input signal. When LOW, data transfers between the CPU and the DUART are enabled on D0 to D7 as controlled by the WRN, RDN and A0 to A3 inputs. When HIGH, places the D0 to D7 lines in the 3-state condition. Write strobe: When LOW and CEN is also LOW, the contents of the data bus is loaded into the addressed register. The transfer occurs on the rising edge of the signal. Read strobe: When LOW and CEN is also LOW, causes the contents of the addressed register to be presented on the data bus. The read cycle begins on the falling edge of RDN. Address inputs: Select the DUART internal registers and ports for read/write operations. Bus configuration: When HIGH or not connected configures the bus interface to the conditions shown in this table. Data bus: Bidirectional 3-state data bus used to transfer commands, data and status between the DUART and the CPU. D0 is the least significant bit. Type Description
WRN
9
3
3
I
RDN
10
4
4
I
A0 A1 A2 A3 RESET
2 4 6 7 38
40 42 44 1 32
44 46 48 1 34
I I I I I
Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR and OPCR), puts OP0 to OP7 in the HIGH state, stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark (HIGH) state. Sets MR pointer to MR1. See Figure 10. Interrupt request: Active LOW, open-drain, output which signals the CPU that one or more of the eight maskable interrupting conditions are true. This pin requires a pull-up device. Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 17). Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 17). If X1/CLK is driven from an external source, this pin must be left open. Channel A receiver serial data input: The least significant bit is received first. See note on drive levels at block diagram (Figure 1). Channel B receiver serial data input: The least significant bit is received first. See note on drive levels at block diagram (Figure 1).
INTRN
24
18
19
O
X1/CLK
36
30
32
I
X2
37
31
33
O
RxDA RxDB
35 11
29 5
31 5
I I
SC28L92_7
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Product data sheet
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NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 2. Symbol TxDA
Pin description for 80xxx bus interface (Intel) ...continued Pin PLCC44 QFP44 HVQFN48 33 28 30 O Channel A transmitter serial data output: The least significant bit is transmitted first. This output is held in the Mark condition when the transmitter is disabled, Idle or when operating in local loopback mode. See note on drive levels at block diagram (Figure 1). Channel B transmitter serial data output: The least significant bit is transmitted first. This output is held in the Mark condition when the transmitter is disabled, Idle, or when operating in local loopback mode. See note on drive levels at block diagram (Figure 1). Output 0: General purpose output or channel A request to send (RTSAN, active LOW). Can be deactivated automatically on receive or transmit. Output 1: General-purpose output or channel B request to send (RTSBN, active LOW). Can be deactivated automatically on receive or transmit. Output 2: General purpose output, or channel A transmitter 1x or 16x clock output, or channel A receiver 1x clock output. Output 3: General purpose output or open-drain, active LOW counter/timer output or channel B transmitter 1x clock output, or channel B receiver 1x clock output. Output 4: General purpose output or channel A open-drain, active LOW, RxA interrupt ISR[1] output. Output 5: General-purpose output or channel B open-drain, active LOW, RxB interrupt ISR[5] output. Output 6: General purpose output or channel A open-drain, active LOW, TxA interrupt ISR[0] output. Output 7: General-purpose output, or channel B open-drain, active LOW, TxB interrupt ISR[4] output. Input 0: General purpose input or channel A clear to send active LOW input (CTSAN). Input 1: General purpose input or channel B clear to send active LOW input (CTSBN). Input 2: General-purpose input or counter/timer external clock input. Input 3: General purpose input or channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Input 4: General purpose input or channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Input 5: General purpose input or channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Input 6: General purpose input or channel B receiver external clock input (RxCB). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Power Supply: 3.3 V 10 % or 5 V 10 % supply input. Type Description
TxDB
13
6
8
O
OP0
32
27
29
O
OP1
14
7
9
O
OP2 OP3
31 15
26 8
28 10
O O
OP4 OP5 OP6 OP7 IP0 IP1 IP2 IP3
30 16 29 17 8 5 40 3
25 9 24 10 2 43 34 41
27 11 26 12 2 47 38 45
O O O O I I I I
IP4
43
37
41
I
IP5
42
36
40
I
IP6
41
35
39
I
VCC
44
38, 39
42
Pwr
SC28L92_7
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Product data sheet
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NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 2. Symbol GND n.c.
Pin description for 80xxx bus interface (Intel) ...continued Pin PLCC44 QFP44 HVQFN48 22 16, 17 18[1] Pwr Ground Not connected 1, 23, 34 23 6, 13, 24, 25, Pwr 36, 37, 43 Type Description
[1]
HVQFN48 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
Table 3. Symbol I/M D0 D1 D2 D3 D4 D5 D6 D7 CEN
Pin description for 68xxx bus interface (Motorola) Pin PLCC44 12 28 18 27 19 26 20 25 21 39 QFP44 HVQFN48 11 22 12 21 13 20 14 19 15 33 7 23 14 22 15 21 16 20 17 35 I I/O I/O I/O I/O I/O I/O I/O I/O I Chip enable: Active LOW input signal. When LOW, data transfers between the CPU and the DUART are enabled on D0 to D7 as controlled by the R/WN and A0 to A3 inputs. When HIGH, places the D0 to D7 lines in the 3-state condition. Read/Write: Input signal. When CEN is LOW, R/WN HIGH input indicates a read cycle; when LOW indicates a write cycle. Interrupt acknowledge: Active LOW input indicating an interrupt acknowledge cycle. Usually asserted by the CPU in response to an interrupt request. When asserted places the interrupt vector on the bus and asserts DACKN. Data transfer acknowledge: A3-state active LOW output asserted in a write, read, or interrupt acknowledge cycle to indicate proper transfer of data between the CPU and the DUART. Address inputs: Select the DUART internal registers and ports for read/write operations. Bus configuration: When LOW configures the bus interface to the conditions shown in this table. Data bus: Bidirectional 3-state data bus used to transfer commands, data and status between the DUART and the CPU. D0 is the least significant bit. Type Description
R/WN IACKN
9 41
3 35
3 39
I I
DACKN
10
4
4
O
A0 A1 A2 A3
2 4 6 7
40 42 44 1 32
44 46 48 1 34
I I I I I
RESETN 38
Reset: A LOW level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0 to OP7 in the HIGH state, stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark (HIGH) state. Sets MR pointer to MR1. See Figure 10.
SC28L92_7
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Product data sheet
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NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 3. Symbol INTRN
Pin description for 68xxx bus interface (Motorola) ...continued Pin PLCC44 24 QFP44 HVQFN48 18 19 O Interrupt request: Active LOW, open-drain, output which signals the CPU that one or more of the eight maskable interrupting conditions are true. This pin requires a pull-up. Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 17). Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 17). If X1/CLK is driven from an external source, this pin must be left open. Channel A receiver serial data input: The least significant bit is received first. See note on drive levels at block diagram (Figure 2). Channel B receiver serial data input: The least significant bit is received first. See note on drive levels at block diagram (Figure 2). Channel A transmitter serial data output: The least significant bit is transmitted first. This output is held in the `mark condition when the transmitter is disabled, idle or when operating in local loopback mode. See note on drive levels at block diagram (Figure 2). Channel B transmitter serial data output: The least significant bit is transmitted first. This output is held in the Mark condition when the transmitter is disabled, idle, or when operating in local loopback mode. See note on drive levels at block diagram (Figure 2). Output 0: General purpose output or channel A request to send (RTSAN, active LOW). Can be deactivated automatically on receive or transmit. Output 1: General purpose output or channel B request to send (RTSBN, active LOW). Can be deactivated automatically on receive or transmit. Output 2: General purpose output, or channel A transmitter 1x or 16x clock output, or channel A receiver 1x clock output. Output 3: General purpose output or open-drain, active LOW counter/timer output or channel B transmitter 1x clock output, or channel B receiver 1x clock output. Output 4: General purpose output or channel A open-drain, active LOW, RxA interrupt ISR [1] output. Output 5: General purpose output or channel B open-drain, active LOW, RxB interrupt ISR[5] output. Output 6: General purpose output or channel A open-drain, active LOW, TxA interrupt ISR[0] output. Output 7: General purpose output, or channel B open-drain, active LOW, TxB interrupt ISR[4] output. Input 0: General purpose input or channel A clear to send active LOW input (CTSAN). Input 1: General purpose input or channel B clear to send active LOW input (CTSBN). Input 2: General purpose input or counter/timer external clock input. Type Description
X1/CLK
36
30
32
I
X2
37
31
33
O
RxDA RxDB TxDA
35 11 33
29 5 28
31 5 30
I I O
TxDB
13
6
8
O
OP0
32
27
29
O
OP1
14
7
9
O
OP2 OP3
31 15
26 8
28 10
O O
OP4 OP5 OP6 OP7 IP0 IP1 IP2
30 16 29 17 8 5 40
25 9 24 10 2 43 34
27 11 26 12 2 47 38
O O O O I I I
SC28L92_7
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Product data sheet
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NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 3. Symbol IP3
Pin description for 68xxx bus interface (Motorola) ...continued Pin PLCC44 3 QFP44 HVQFN48 41 45 I Input 3: General purpose input or channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Input 4: General purpose input or channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Input 5: General purpose input or channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Power Supply: 3.3 V 10 % or 5 V 10 % supply input. Ground Not connected Type Description
IP4
43
37
41
I
IP5
42
36
40
I
VCC GND n.c.
44 22
38, 39 16, 17
42 18[1] 6, 13, 24, 25, 36, 37, 43
Pwr Pwr -
1, 23, 34 23
[1]
HVQFN48 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
6. Functional description
6.1 Block diagram
The SC28L92 DUART consists of the following eight major sections: data bus buffer, operation control, interrupt control, timing, communications channels A and B, input port and output port. Refer to Section 4 "Block diagram".
6.1.1 Data bus buffer
The data bus buffer provides the interface between the external and internal data buses. It is controlled by the operation control block to allow read and write operations to take place between the controlling CPU and the DUART.
6.1.2 Operation control
The operation control logic receives operation commands from the CPU and generates appropriate signals to internal sections to control device operation. It contains address decoding and read and write circuits to permit communications with the microprocessor via the data bus.
6.1.3 Interrupt control
A single active LOW interrupt output (INTRN) is provided which is activated upon the occurrence of any of eight internal events. Associated with the interrupt system are the Interrupt Mask Register (IMR) and the Interrupt Status Register (ISR). The IMR can be programmed to select only certain conditions to cause INTRN to be asserted. The ISR can be read by the CPU to determine all currently active interrupting conditions. Outputs OP3 to OP7 can be programmed to provide discrete interrupt outputs for the transmitter,
SC28L92_7
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
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NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
receivers, and counter/timer. When OP3 to OP7 are programmed as interrupts, their output buffers are changed to the open-drain active LOW configuration. The OP pins may be used for DMA and modem control as well (see Section 7.4).
6.1.4 FIFO configuration
Each receiver and transmitter has a 16 byte FIFO. These FIFOs may be configured to operate at a fill capacity of either 8 bytes or 16 bytes. This feature may be used if it is desired to operate the SC28L92 in strict compliance with the SC26C92. The 8 byte or 16 byte mode is controlled by the MR0A[3] bit. A logic 0 value for this bit sets the 8-bit mode (the default); a logic 1 sets the 16 byte mode. MR0A bit 3 sets the FIFO size for both channels. The FIFO fill interrupt level automatically follow the programming of the MR0A[3] bit. See Table 25 and Table 26.
6.1.5 68xxx mode
When the I/M pin is connected to GND (ground), the operation of the SC28L92 switches to the bus interface compatible with the Motorola bus interfaces. Several of the pins change their function as follows: IP6 becomes IACKN input RDN becomes DACKN WRN becomes R/WN The interrupt vector is enabled and the interrupt vector will be placed on the data bus when IACKN is asserted LOW. The interrupt vector register is located at address 0xC. The contents of this register are set to 0x0F on the application of RESETN. The generation of DACKN uses two positive edges of the X1 clock as the DACKN delay from the falling edge of CEN. If the CEN is withdrawn before two edges of the X1 clock occur, the generation of DACKN is terminated. Systems not strictly requiring DACKN may use the 68xxx mode with the bus timing of the 80xxx mode greatly decreasing the bus cycle time.
6.2 Timing circuits
6.2.1 Crystal clock
The timing block consists of a crystal oscillator, a baud rate generator, a programmable 16-bit counter/timer, and four clock selectors. The crystal oscillator operates directly from a crystal connected across the X1/CLK and X2 inputs. If an external clock of the appropriate frequency is available, it may be connected to X1/CLK. The clock serves as the basic timing reference for the Baud Rate Generator (BRG), the counter/timer, and other internal circuits. A clock signal within the limits specified in Section 10 "Dynamic characteristics" must always be supplied to the DUART. If an external clock is used instead of a crystal, X1 should be driven using a configuration similar to the one in Figure 17. Nominal crystal rate is 3.6864 MHz. Rates up to 8 MHz may be used.
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6.2.2 Baud rate generator
The baud rate generator operates from the oscillator or external clock input at the X1 input and is capable of generating 28 commonly used data communications baud rates ranging from 50 kBd to 38.4 kBd. Programming bit 0 of MR0 to a logic 1 gives additional baud rates of 57.6 kBd, 115.2 kBd and 230.4 kBd (500 kHz with X1 at 8.0 MHz). Note that the MR0A[2:0] control this change and that the change applies to both channels. MR0B[2:0] are reserved. The baud rates are based on an input frequency of 3.6864 MHz. Changing the X1 frequency will change all baud rates by ratio of 3.6864 MHz to the new frequency. All rates generated by the BRG will be in the 16x mode. The clock outputs from the BRG are at 16x the actual baud rate. The counter/timer can be used as a timer to produce a 16x clock for any other baud rate by counting down the crystal clock or an external clock. The four clock selectors allow the independent selection, for each receiver and transmitter, of any of these baud rates or external timing signal. The use of the counter/timer also requires the generation of a frequency 16x of the baud rate. See Section 6.2.3.
6.2.3 Counter/timer
The Counter/timer is a 16-bit programmable divider that operates in one of three modes: counter, timer and time-out. In the timer mode it generates a square wave. In the counter mode it generates a time delay. In the time-out mode it monitors the time between received characters. The C/T uses the numbers loaded into the Counter/Timer Lower Register (CTLR) and the Counter/Timer Upper Register (CTUR) as its divisor. The counter/timer clock source and mode of operation (counter or timer) is selected by the Auxiliary Control Register bits 6 to 4 (ACR[6:4]). The output of the counter/timer may be used for a baud rate and/or may be output to the OP pins for some external function that may be totally unrelated to data transmission. The counter/timer also sets the counter/timer ready bit in the Interrupt Status Register (ISR) when its output transitions from logic 1 to logic 0. A register read address (see Table 4) is reserved to issue a start counter/timer command and a second register read address is reserved to issue a stop command. The value of D[7:0] is ignored. The START command always loads the contents of CTUR, CTLR to the counting registers. The STOP command always resets the ISR[3] bit in the interrupt status register.
6.2.4 Timer mode
In the timer mode a symmetrical square wave is generated whose half period is equal in time to division of the selected counter/timer clock frequency by the 16-bit number loaded in the CTLR CTUR. Thus, the frequency of the counter/timer output will be equal to the counter/timer clock frequency divided by twice the value of the CTUR CTLR. While in the timer mode the ISR bit 3 (ISR[3]) will be set each time the counter/timer transitions from logic 1 to logic 0 (HIGH-to-LOW). This continues regardless of issuance of the stop counter command. ISR[3] is reset by the stop counter command. Note: Reading of the CTU and CTL registers in the timer mode is not meaningful. When the C/T is used to generate a baud rate and the C/T is selected through the CSR then the receivers and/or transmitter will be operating in the 16x mode. Calculation for the number n to program the counter/timer upper and lower registers is shown in Equation 1. The value of the divisor n is
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counter/timer input clock n = -------------------------------------------------------------------------2 x 16 x ( desired baud rate )
(1)
Often this division will result in a non-integer number; 26.3 for example. One may only program integer numbers to a digital divider. Therefore 26 (0x1A) would be chosen. If 26.7 were the result of the division, then 27 (0x1B) would be chosen. This gives a baud rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage error of 1.14 % or 1.12 % respectively, well within the ability of the asynchronous mode of operation. Higher input frequency to the counter reduces the error effect of the fractional division.
6.2.5 Counter mode
In the counter mode the counter/timer counts the value of the CTLR CTUR down to zero and then sets the ISR[3] bit and sets the counter/timer output from 1 to 0. It then rolls over to 65,365 and continues counting with no further observable effect. Reading the C/T in the counter mode outputs the present state of the C/T. If the C/T is not stopped, a read of the C/T may result in changing data on the data bus.
6.2.6 Time-out mode
The time-out mode uses the received data stream to control the counter. The time-out mode forces the C/T into the timer mode. Each time a received character is transferred from the shift register to the Rx FIFO, the counter is restarted. If a new character is not received before the counter reaches zero count, the counter ready bit is set, and an interrupt can be generated. This mode can be used to indicate when data has been left in the Rx FIFO for more than the programmed time limit. If the receiver has been programmed to interrupt the CPU when the receive FIFO is full, and the message ends before the FIFO is full, the CPU will not be interrupted for the remaining characters in the Rx FIFO. By programming the C/T such that it would time-out in just over one character time, the above situation could be avoided. The processor would be interrupted any time the data stream had stopped for more than one character time. Note: This is very similar to the watchdog time of MR0. The difference is in the programmability of the delay time and that the watchdog timer is restarted by either a receiver load to the Rx FIFO or a system read from it. This mode is enabled by writing the appropriate command to the command register. Writing 0xA to CRA or CRB will invoke the time-out mode for that channel. Writing 0xC to CRA or CRB will disable the time-out mode. Only one receiver should use this mode at a time. However, if both are on, the time-out occurs after both receivers have been inactive for the time-out period. The start of the C/T will be on the logic OR of the two receivers. The time-out mode disables the regular start counter or stop counter commands and puts the C/T into counter mode under the control of the received data stream. Each time a received character is transferred from the shift register to the Rx FIFO, the C/T is stopped after one C/T clock, reloaded with the value in CTUR and CTLR and then restarted on the next C/T clock. If the C/T is allowed to end the count before a new character has been received, the counter ready bit, ISR[3], will be set. If IMR[3] is set, this will generate an interrupt. Since receiving a character restarts the C/T, the receipt of a character after the C/T has timed out will clear the counter ready bit, ISR[3], and the interrupt. Invoking the Set Time-out Mode On command, CRx = 0xA, will also clear the counter ready bit and stop the counter until the next character is received. The counter/timer is controlled with six commands: Start/Stop C/T, Read/Write Counter/Timer lower register and Read/Write
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Counter/Timer upper register. These commands have slight differences depending on the mode of operation. Please see the detail of the commands in Section 7.3.3 "Command registers".
6.2.7 Time-out mode caution
When operating in the special time-out mode, it is possible to generate what appears to be a false interrupt, i.e., an interrupt without a cause. This may result when a time-out interrupt occurs and then, before the interrupt is serviced, another character is received, i.e., the data stream has started again. (The interrupt latency is longer than the pause in the data stream.) In this case, when a new character has been received, the counter/timer will be restarted by the receiver, thereby withdrawing its interrupt. If, at this time, the interrupt service begins for the previously seen interrupt, a read of the ISR will show the Counter Ready bit not set. If nothing else is interrupting, this read of the ISR will return a 0x00 character. This action may present the appearance of a spurious interrupt.
6.2.8 Communications channels A and B
Each communications channel of the SC28L92 comprises a full-duplex asynchronous receiver/transmitter (UART). The operating frequency for each receiver and transmitter can be selected independently from the baud rate generator, the counter/timer, or from an external input. The transmitter accepts parallel data from the CPU, converts it to a serial bit stream, inserts the appropriate start, stop, and optional parity bits and outputs a composite serial stream of data on the TxD output pin. The receiver accepts serial data on the RxD pin, converts this serial input to parallel format, checks for start bit, stop bit, parity bit (if any), or break condition and sends an assembled character to the CPU via the receive FIFO. Three status bits (break received, framing and parity errors) are also FIFOed with each data character.
6.2.9 Input port
The inputs to this unlatched 7-bit (6-bit for 68xxx mode) port can be read by the CPU by performing a read operation at address 0xD. A HIGH input results in a logic 1 while a LOW input results in a logic 0. D7 will always read as a logic 1. The pins of this port can also serve as auxiliary inputs to certain portions of the DUART logic, modem and DMA. Four change-of-state detectors are provided which are associated with inputs IP3, IP2, IP1 and IP0. A HIGH-to-LOW or LOW-to-HIGH transition of these inputs, lasting longer than 25 s to 50 s, will set the corresponding bit in the input port change register. The bits are cleared when the register is read by the CPU. Any change of state can also be programmed to generate an interrupt to the CPU. The input port change of state detection circuitry uses a 38.4 kHz sampling clock derived from one of the baud rate generator taps. This results in a sampling period of slightly more than 25 s (this assumes that the clock input is 3.6864 MHz). The detection circuitry, in order to guarantee that a true change in level has occurred, requires two successive samples at the new logic level be observed. As a consequence, the minimum duration of the signal change is 25 s if the transition occurs coincident with the first sample pulse. The 50 s time refers to the situation in which the change of state is just missed and the first change of state is not detected until 25 s later.
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6.2.10 Output port
The output ports are controlled from six places: the OPCR, OPR, MR, Command, SOPR and ROPR registers. The OPCR register controls the source of the data for the output ports OP2 through OP7. The data source for output ports OP0 and OP1 is controlled by the MR and CR registers. When the OPR is the source of the data for the output ports, the data at the ports is inverted from that in the OPR register. The content of the OPR register is controlled by the set output port bits command and the reset output bits command. These commands are at 0xE and 0xF, respectively. When these commands are used, action takes place only at the bit locations where ones exist. For example, a one in bit location 5 of the data word used with the set output port bits command will result in OPR5 being set to one. The OP5 would then be set to zero (VSS). Similarly, a one in bit position 5 of the data word associated with the reset output ports bits command would set OPR5 to zero and, hence, the pin OP5 to a one (VDD). These pins along with the IP pins and their change-of-state detectors are often used for modem and DMA control.
6.3 Operation
6.3.1 Transmitter
The SC28L92 is conditioned to transmit data when the transmitter is enabled through the command register. The SC28L92 indicates to the CPU that it is ready to accept a character by setting the TxRDY bit in the status register. This condition can be programmed to generate an interrupt request at OP6 or OP7 and INTRN. When the transmitter is initially enabled the TxRDY and TxEMPT bits will be set in the status register. When a character is loaded to the transmit FIFO the TxEMPT bit will be reset. The TxEMPT will not set until: 1) the transmit FIFO is empty and the transmit shift register has finished transmitting the stop bit of the last character written to the transmit FIFO, or 2) the transmitter is disabled and then re-enabled. The TxRDY bit is set whenever the transmitter is enabled and the Tx FIFO is not full. Data is transferred from the holding register to transmit shift register when it is idle or has completed transmission of the previous character. Characters cannot be loaded into the Tx FIFO while the transmitter is disabled. The transmitter converts the parallel data from the CPU to a serial bit stream on the TxD output pin. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is sent first. Following the transmission of the stop bits, if a new character is not available in the Tx FIFO, the TxD output remains HIGH and the TxEMT bit in the Status Register (SR) will be set to 1. Transmission resumes and the TxEMT bit is cleared when the CPU loads a new character into the Tx FIFO. If the transmitter is disabled it continues operating until the character currently being transmitted and any characters in the Tx FIFO, including parity and stop bits, have been transmitted. New data cannot be loaded to the Tx FIFO when the transmitter is disabled. When the transmitter is reset it stops sending data immediately. The transmitter can be forced to send a break (a continuous LOW condition) by issuing a START BREAK command via the CR register. The break is terminated by a STOP BREAK command or a transmitter reset.
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If CTS option is enabled (MR2[4] = 1), the CTS input at IP0 or IP1 must be LOW in order for the character to be transmitted. The transmitter will check the state of the CTS input at the beginning of each character transmitted. If it is found to be HIGH, the transmitter will delay the transmission of any following characters until the CTS has returned to the LOW state. CTS going HIGH during the serialization of a character will not affect that character. The transmitter can also control the RTSN outputs, OP0 or OP1 via MR2[5]. When this mode of operation is set, the meaning of the OP0 or OP1 signals will usually be end of message. See description of bit MR2[5] in Table 30 "MR2A - Mode Register 2 channel A (address 0x0) bit description" for more detail. This feature may be used to automatically turn around a transceiver in simplex systems.
6.3.2 Receiver
The SC28L92 is conditioned to receive data when enabled through the command register. The receiver looks for a HIGH-to-LOW (mark-to-space) transition of the start bit on the RxD input pin. If a transition is detected, the state of the RxD pin is sampled each 16x clock for 7 clocks to 12 clocks (16x clock mode) or at the next rising edge of the bit time clock (1x clock mode). If RxD is sampled HIGH, the start bit is invalid and the search for a valid start bit begins again. If RxD is still LOW, a valid start bit is assumed and the receiver continues to sample the input at one bit time intervals at the theoretical center of the bit, until the proper number of data bits and parity bit (if any) have been assembled, and one stop bit has been detected. The least significant bit is received first. The data is then transferred to the receive FIFO and the RxRDY bit in the SR is set to a 1. This condition can be programmed to generate an interrupt at OP4 or OP5 and INTRN. If the character length is less than 8 bits, the most significant unused bits in the Rx FIFO are set to zero. After the stop bit is detected, the receiver will immediately look for the next start bit. However, if a non-zero character was received without a stop bit (framing error) and RxD remains LOW for one half of the bit period after the stop bit was sampled, then the receiver operates as if a new start bit transition had been detected at that point (one-half bit time after the stop bit was sampled). The parity error, framing error and overrun error (if any) are strobed into the SR from the next byte to be read from the Rx FIFO. If a break condition is detected (RxD is LOW for the entire character including the stop bit), a character consisting of all zeros will be loaded into the Rx FIFO and the received break bit in the SR is set to 1. The RxD input must return to HIGH for two (2) clock edges of the X1 crystal clock for the receiver to recognize the end of the break condition and begin the search for a start bit. This will usually require a HIGH time of one X1 clock period or 3 X1 edges since the clock of the controller is not synchronous to the X1 clock.
6.3.3 Transmitter reset and disable
Note the difference between transmitter disable and reset. A transmitter reset stops transmitter action immediately, clears the transmitter FIFO and returns the idle state. A transmitter disable withdraws the transmitter interrupts but allows the transmitter to continue operation until all bytes in its FIFO and shift register have been transmitted including the final stop bits. It then returns to its idle state.
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6.3.4 Receiver FIFO
The Rx FIFO consists of a First-In-First-Out (FIFO) stack with a capacity of 8 or 16 characters. Data is loaded from the receive shift register into the topmost empty position of the FIFO. The RxRDY bit in the status register is set whenever one or more characters are available to be read, and a FFULL status bit is set if all 8 or 16 stack positions are filled with data. Either of these bits can be selected to cause an interrupt. A read of the Rx FIFO outputs the data at the top of the FIFO. After the read cycle, the data FIFO and its associated status bits (see Section 6.3.5) are popped thus emptying a FIFO position for new data. A disabled receiver with data in its FIFO may generate an interrupt (see Section 6.3.5). Its status bits remain active and its watchdog, if enabled, will continue to operate.
6.3.5 Receiver status bits
In addition to the data word, three status bits (parity error, framing error and received break) are also appended to each data character in the FIFO. The overrun error, MR1[5], is not FIFOed. Status can be provided in two ways, as programmed by the error mode control bit in the mode register. In the character mode, status is provided on a character-by-character basis; the status applies only to the character at the top of the FIFO. In the block mode, the status provided in the SR for these three bits is the logic OR of the status for all characters coming to the top of the FIFO since the last reset error from the command register was issued. In either mode reading the SR does not affect the FIFO. The FIFO is popped only when the Rx FIFO is read. Therefore the status register should be read prior to reading the FIFO. If the FIFO is full when a new character is received, that character is held in the receive shift register until a FIFO position is available. If an additional character is received while this state exits, the contents of the FIFO are not affected; the character previously in the shift register is lost and the overrun error status bit (SR[4]) will be set upon receipt of the start bit of the new (overrunning) character. The receiver can control the deactivation of RTS. If programmed to operate in this mode, the RTSN output will be negated when a valid start bit was received and the FIFO is full. When a FIFO position becomes available, the RTSN output will be reasserted (set LOW) automatically. This feature can be used to prevent an overrun, in the receiver, by connecting the RTSN output to the CTSN input of the transmitting device. If the receiver is disabled, the FIFO characters can be read. However, no additional characters can be received until the receiver is enabled again. If the receiver is reset, the FIFO and all of the receiver status, and the corresponding output ports and interrupt are reset. No additional characters can be received until the receiver is enabled again.
6.3.6 Receiver reset and disable
Receiver disable stops the receiver immediately. Data being assembled in the receiver shift register is lost. Data and status in the FIFO is preserved and may be read. A re-enable of the receiver after a disable will cause the receiver to begin assembling characters at the next start bit detected.
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A receiver reset will discard the present shift register date, reset the receiver ready bit (RxRDY), clear the status of the byte at the top of the FIFO and realign the FIFO read/write pointers.
6.3.7 Watchdog
A watchdog timer is associated with each receiver. Its interrupt is enabled by MR0[7]. The purpose of this timer is to alert the control processor that characters are in the Rx FIFO which have not been read. This situation may occur at the end of a transmission when the last few characters received are not sufficient to cause an interrupt. This counter times out after 64 bit times. It is reset each time a character is transferred from the receiver shift register to the Rx FIFO or a read of the Rx FIFO is executed.
6.3.8 Receiver time-out mode
In addition to the watchdog timer described in Section 6.3.7, the counter/timer may be used for a similar function. Its programmability, of course, allows much greater precision of time-out intervals. The time-out mode uses the received data stream to control the counter. Each time a received character is transferred from the shift register to the Rx FIFO, the counter is restarted. If a new character is not received before the counter reaches zero count, the counter ready bit is set, and an interrupt can be generated. This mode can be used to indicate when data has been left in the Rx FIFO for more than the programmed time limit. Otherwise, if the receiver has been programmed to interrupt the CPU when the receive FIFO is full, and the message ends before the FIFO is full, the CPU may not know there is data left in the FIFO. The CTU and CTL value would be programmed for just over one character time, so that the CPU would be interrupted as soon as it has stopped receiving continuous data. This mode can also be used to indicate when the serial line has been marking for longer than the programmed time limit. In this case, the CPU has read all of the characters from the FIFO, but the last character received has started the count. If there is no new data during the programmed time interval, the counter ready bit will get set, and an interrupt can be generated. The time-out mode is enabled by writing the appropriate command to the command register. Writing 0xA to CRA or CRB will invoke the time-out mode for that channel. Writing 0xC to CRA or CRB will disable the time-out mode. The time-out mode should only be used by one channel at once, since it uses the C/T. If, however, the time-out mode is enabled from both receivers, the time-out will occur only when both receivers have stopped receiving data for the time-out period. CTU and CTL must be loaded with a value greater than the normal receive character period. The time-out mode disables the regular start counter or stop counter commands and puts the C/T into counter mode under the control of the received data stream. Each time a received character is transferred from the shift register to the Rx FIFO, the C/T is stopped after one C/T clock, reloaded with the value in CTU and CTL and then restarted on the next C/T clock. If the C/T is allowed to end the count before a new character has been received, the counter ready bit, ISR[3], will be set. If IMR[3] is set, this will generate an interrupt. Receiving a character after the C/T has timed out will clear the counter ready bit, ISR[3], and the interrupt. Invoking the set time-out mode on command, CRx = 0xA, will also clear the counter ready bit and stop the counter until the next character is received.
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6.3.9 Time-out mode caution
When operating in the special time-out mode, it is possible to generate what appears to be a false interrupt, i.e., an interrupt without a cause. This may result when a time-out interrupt occurs and then, before the interrupt is serviced, another character is received, i.e., the data stream has started again. (The interrupt latency is longer than the pause in the data stream.) In this case, when a new character has been receiver, the counter/timer will be restarted by the receiver, thereby withdrawing its interrupt. If, at this time, the interrupt service begins for the previously seen interrupt, a read of the ISR will show the counter ready bit not set. If nothing else is interrupting, this read of the ISR will return a 0x00 character.
6.3.10 Multi-drop mode (9-bit or wake-up)
The DUART is equipped with a wake-up mode for multi-drop applications. This mode is selected by programming bits MR1A[4:3] or MR1B[4:3] to 11 for channels A and B, respectively. In this mode of operation, a master station transmits an address character followed by data characters for the addressed slave station. The slave stations, with receivers that are normally disabled, examine the received data stream and wake-up the CPU (by setting RxRDY) only upon receipt of an address character. The CPU compares the received address to its station address and enables the receiver if it wishes to receive the subsequent data characters. Upon receipt of another address character, the CPU may disable the receiver to initiate the process again. A transmitted character consists of a start bit, the programmed number of data bits, and Address/Data (A/D) bit, and the programmed number of stop bits. The polarity of the transmitted A/D bit is selected by the CPU by programming bit MR1A[2]/MR1B[2]. MR1A[2]/MR1B[2] = 0 transmits a zero in the A/D bit position, which identifies the corresponding data bits as data while MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position, which identifies the corresponding data bits as an address. The CPU should program the mode register prior to loading the corresponding data bits into the Tx FIFO. In this mode, the receiver continuously looks at the received data stream, whether it is enabled or disabled. If disabled, it sets the RxRDY status bit and loads the character into the Rx FIFO if the received A/D bit is a one (address tag), but discards the received character if the received A/D bit is a zero (data tag). If enabled, all received characters are transferred to the CPU via the Rx FIFO. In either case, the data bits are loaded into the data FIFO while the A/D bit is loaded into the status FIFO position normally used for parity error (SRA[5] or SRB[5]). Framing error, overrun error, and break detect operate normally whether or not the receive is enabled.
7. Programming
7.1 Register overview
The operation of the DUART is programmed by writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU. The addressing of the registers is described in Table 4. The contents of certain control registers are initialized to zero on RESET. Care should be exercised if the contents of a register are changed during operation, since certain changes may cause operational problems.
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For example, changing the number of bits per character while the transmitter is active may cause the transmission of an incorrect character. In general, the contents of the MR, the CSR, and the OPCR should only be changed while the receiver(s) and transmitter(s) are not enabled, and certain changes to the ACR should only be made while the C/T is stopped. Each channel has three mode registers (MR0, MR1 and MR2) which control the basic configuration of the channel. Access to these registers is controlled by independent MR address pointers. These pointers are set to 0x0 or 0x1 by MR control commands in the command register Miscellaneous Commands. Each time the MR registers are accessed the MR pointer increments, stopping at MR2. It remains pointing to MR2 until set to 0x0 or 0x1 via the miscellaneous commands of the command register. The pointer is set to 0x1 on reset for compatibility with previous Philips Semiconductors UART software. Mode, command, clock select, and status registers are duplicated for each channel to provide total independent operation and control. Refer to Section 7.2 for register bit overview. The reserved registers at addresses 0x2 and 0xA should never be read during normal operation since they are reserved for internal diagnostics.
Table 4. 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
[1]
SC28L92 register addressing READ (RDN = 0), WRITE (WRN = 0)[1] Read operation (RDN = 0 and CEN = 0) 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 Mode Register A (MR0A, MR1A, MR2A) Status Register A (SRA) reserved Rx Holding Register A (RxFIFOA) Input Port Change Register (IPCR) Interrupt Status Register (ISR) Counter/Timer Upper (CTU) Counter/Timer Lower (CTL) Mode Register B (MR0B, MR1B, MR2B) Status Register B (SRB) reserved Rx Holding Register B (RxFIFOB) Interrupt vector (68xxx mode) Miscellaneous register (Intel mode), IVR Motorola mode Input Port Register (IPR) start counter command stop counter command Write operation (WRN = 0 and CEN = 0) Mode Register A (MR0A, MR1A, MR2A) Clock Select Register A (CSRA) Command Register A (CRA) Tx Holding Register A (TxFIFOA) Auxiliary Control Register (ACR) Interrupt Mask Register (IMR) C/T Upper Preset Register (CTPU) C/T Lower Preset Register (CTPL) Mode Register B (MR0B, MR1B, MR2B) Clock Select Register B (CSRB) Command Register B (CRB) Tx Holding Register B (TxFIFOB) Interrupt vector (68xxx mode) Miscellaneous register (Intel mode), IVR Motorola mode Output Port Configuration Register (OPCR) Set Output Port Bits Command (SOPR) Reset output Port Bits Command (ROPR) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1
Binary address 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1
The three MR registers are accessed via the MR Pointer and Commands 0x1n and 0xBn (where n = represents receiver and transmitter enable bits).
Table 5.
Registers for channels A and B Channel A register MRnA SRA CSRA Channel B register MRnB SRB CSRB Access R/W R only W only
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Register name Mode Register Status Register Clock Select
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Registers for channels A and B ...continued Channel A register CRA RxFIFOA TxFIFOA Channel B register CRB RxFIFOB TxFIFOB Access W only R only W only
Table 5.
Register name Command Register Receiver FIFO Transmitter FIFO Table 6.
Registers supporting both channels Mnemonic IPCR ACR ISR IMR CTU CTL CTPU CTPL IPR OPCR SOPR ROPR IVR/GP Access R W R W R R W W R W W W R/W
Register name Input Port Change Register Auxiliary Control Register Interrupt Status Register Interrupt Mask Register Counter/Timer Upper value Counter/Timer Lower value Counter/Timer Preset Upper Counter/Timer Preset Lower Input Port Register Output Configuration Register Set Output Port Reset Output Port Interrupt vector or GP register
7.2 Condensed register bit formats
Table 7. 7 RxWATCHDOG MR0 - Mode Register 0 6 RxINT[2] 5 TxINT[1:0] 4 3 FIFOSIZE 2 BAUDRATE EXTENDED II 1 TEST2 0 BAUDRATE EXTENDED I
Table 8. 7 RxRTS control Table 9. 7
MR1 - Mode Register 1 6 RxINT[1] 5 ERRORMODE 4 3 2 PARITYTYPE 1 0 PARITYMODE bits per character
MR2 - Mode Register 2 6 channel mode 5 RTSN Control Tx 4 CTSN Enable Tx 3 2 stop bit length 1 0
Table 10. 7
CSR - Clock Select Register 6 5 4 3 2 1 0 receiver clock select code transmitter clock select code
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Table 11. 7
CR - Command Register 6 5 4 3 disable Tx 2 enable Tx 1 disable Rx 0 enable Rx channel command code
Table 12. 7 received break Table 13. 7
SR - channel Status Register 6 framing error 5 parity error 4 overrun error 3 TxEMT 2 TxRDY 1 RxFULL 0 RxRDY
IMR - Interrupt Mask Register (enables interrupts) 6 change break B 5 RxRDYB 4 TxRDTYB 3 2 1 RxRDYA 0 TxRDYA counter ready change break A
change input port Table 14. 7 input port change Table 15. 7
ISR - Interrupt Status Register 6 change break B 5 RxRDYB FFULLB 4 TxRDTYB 3 2 1 RxRDYA FFULLA 0 TxRDYA counter ready change break A
CTPU - Counter/Timer Preset Register, Upper 6 5 4 3 2 1 0 8 MSB of the BRG timer divisor
Table 16. 7
CTPL - Counter/Timer Preset Register, Lower 6 5 4 3 2 1 0 8 LSB of the BRG timer divisor
Table 17. 7 BRG set select Table 18. 7 delta IP3 Table 19. 7
ACR - Auxiliary Control Register and change of state control 6 5 4 3 enable IP3 COS interrupt 2 enable IP2 COS interrupt 1 enable IP1 COS interrupt 0 enable IP0 COS interrupt counter/timer mode and clock source select (see Table 54 on page 44) IPCR - Input Port Change Register 6 delta IP2 5 delta IP1 4 delta IP0 3 state of IP3 2 state of IP2 1 state of IP1 0 state of IP0
IPR - Input Port Register 6 state of IP6 5 state of IP5 4 state of IP4 3 state of IP3 2 state of IP2 1 state of IP1 0 state of IP0
state of IP7 Table 20. 7 set OP7
SOPR - Set Output Port bits Register (SOPR) 6 set OP6 5 set OP5 4 set OP4 3 set OP3 2 set OP2 1 set OP1 0 set OP0
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Table 21. 7
ROPR - Reset Output Port bits Register (ROPR) 6 reset OP6 5 reset OP5 4 reset OP4 3 reset OP3 2 reset OP2 1 reset OP1 0 reset OP0
reset OP7
Table 22. OPCR - Output Port Configuration Register OP1 and OP0 are the RTSN output and are controlled by the MR register 7 configure OP7 6 configure OP6 5 configure OP5 4 configure OP4 3 configure OP3 2 configure OP3 1 configure OP2 0 configure OP2
7.3 Register descriptions
7.3.1 Mode registers
7.3.1.1 Mode Register 0 channel A (MR0A)
Table 23. MR0A - Mode Register 0 channel A (address 0x0) bit allocation MR0 is accessed by setting the MR pointer to logic 0 via the command register command B. 7 RxWATCHDOG 6 RxINT[2] 5 TxINT[1:0] 4 3 FIFOSIZE 2 BAUDRATE EXTENDED II 1 TEST2 0 BAUDRATE EXTENDED I
Table 24. Bit 7
MR0A - Mode Register 0 channel A (address 0x0) bit description Symbol RxWATCHDOG Description This bit controls the receiver watchdog timer. 0 = disable 1 = enable When enabled, the watchdog timer will generate a receiver interrupt if the receiver FIFO has not been accessed within 64 bit times of the receiver 1x clock. The watchdog timer is used to alert the control processor that data is in the Rx FIFO that has not been read. This situation will occur when the byte count of the last part of a message is not large enough to generate an interrupt. The watchdog timer presents itself as a receiver interrupt with the RxRDY bit set in SR and ISR.
6
RxINT[2]
Bit 2 of receiver FIFO interrupt level. This bit along with bit 6 of MR1 sets the fill level of the FIFO that generates the receiver interrupt. Note that this control is split between MR0 and MR1. This is for backward compatibility to the SC26C92 and SCC2681. For the receiver these bits control the number of FIFO positions filled when the receiver will attempt to interrupt. After the reset the receiver FIFO is empty. The default setting of these bits cause the receiver to attempt to interrupt when it has one or more bytes in it; see Table 25.
5 and 4
TxINT[1:0]
Transmitter interrupt fill level. For the transmitter these bits control the number of FIFO positions empty when the receiver will attempt to interrupt; see Table 26. After the reset the transmit FIFO has 8 bytes empty. It will then attempt to interrupt as soon as the transmitter is enabled. The default setting (TxINT[1:0] = 00) condition the transmitter to attempt to interrupt only when it is completely empty. As soon as one byte is loaded, it is no longer empty and hence will withdraw its interrupt request.
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MR0A - Mode Register 0 channel A (address 0x0) bit description ...continued Symbol FIFOSIZE Description FIFO size for channel A and channel B. Selects the FIFO depth at 8-byte or 16-byte. 0 = 8 bytes 1 = 16 bytes
Table 24. Bit 3
2 1 0
BAUDRATE EXTENDED I TEST2 BAUDRATE EXTENDED II
Bits MR0[2:0] are used to select one of the six baud rate groups. See Table 35 for the group organization. 000 = Normal mode 001 = Extended mode I 100 = Extended mode II Other combinations of MR0[2:0] should not be used.
Table 25.
Receiver FIFO interrupt fill level[1] Interrupt condition 1 or more bytes in FIFO (RxRDY) 3 or more bytes in FIFO 6 or more bytes in FIFO 8 bytes in FIFO (RxFULL) 1 or more bytes in FIFO (RxRDY) 8 or more bytes in FIFO 12 or more bytes in FIFO 16 bytes in FIFO (RxFULL)
RxINT[2:1] (bits MR0[6] and MR1[6]) FIFOSIZE = 0 (8 bytes) 00 01 10 11 FIFOSIZE = 1 (16 bytes) 00 01 10 11
[1]
Interrupt fill level must be set when the transmit and receive FIFOs are empty, otherwise the new level takes effect only after a read or a write to the FIFO.
Table 26.
Transmitter FIFO interrupt fill level[1] Interrupt condition 8 bytes empty (TxEMPTY) 4 or more bytes empty 6 or more bytes empty 1 or more bytes empty (TxRDY) 16 bytes empty (TxEMPTY) 8 or more bytes empty 12 or more bytes empty 1 or more bytes empty (TxRDY)
TxINT[1:0] (bits MR0[5:4]) FIFOSIZE = 0 (8 bytes) 00 01 10 11 FIFOSIZE = 1 (16 bytes) 00 01 10 11
[1]
Interrupt fill level must be set when the transmit and receive FIFOs are empty, otherwise the new level takes effect only after a read or a write to the FIFO.
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7.3.1.2
Mode Register 1 channel A (MR1A)
Table 27. MR1A - Mode Register 1 channel A (address 0x0) bit allocation MR1A is accessed when the channel A MR pointer points to MR1. The pointer is set to MR1 by RESET or by a set pointer command applied via CR command 1. After reading or writing MR1A, the pointer will point to MR2A[1]. 7 RxRTS control
[1]
6 RxINT[1]
5 ERRORMODE
4
3
2 PARITYTYPE
1
0
PARITYMODE
bits per character
In block error mode, block error conditions must be cleared by using the error reset command (command 0x4) or a receiver reset.
Table 28. Bit 7
MR1A - Mode Register 1 channel A (address 0x0) bit description Symbol RxRTS Description Channel A receiver request to send control (flow control). This bit controls the deactivation of the RTSAN output (OP0) by the receiver. This output is normally asserted by setting OPR[0] and negated by resetting OPR[0]. Proper automatic operation of flow control requires OPR[0] (channel A) or OPR[1] (channel B) to be set to logic 1. 0 = No RTS control 1 = RTS control RxRTS = 1 causes RTSAN to be negated (OP0 is driven to a logic 1 [VCC]) upon receipt of a valid start bit if the channel A FIFO is full. This is the beginning of the reception of the 9th byte. If the FIFO is not read before the start of the 10th or 17th byte, an overrun condition will occur and the 10th or 17th or 17th byte will be lost. However, the bit in OPR[0] is not reset and RTSAN will be asserted again when an empty FIFO position is available. This feature can be used for flow control to prevent overrun in the receiver by using the RTSAN output signal to control the CTSN input of the transmitting device.
6 5
RxINT[1] ERRORMODE
Bit 1 of the receiver interrupt control. See description of RxINT[2] in Table 25 and Table 26. Channel A error mode select. 0 = character 1 = block This bit selects the operating mode of the three FIFOed status bits (FE, PE, received break) for channel A. In the character mode, status is provided on a character-by-character basis; the status applies only to the character at the top of the FIFO. In the block mode, the status provided in the SR for these bits is the accumulation (logic OR) of the status for all characters coming to the top of the FIFO since the last reset error command for channel A was issued.
4 and 3
PARITYMODE
Channel A parity mode select 00 = with parity 01 = force parity 10 = no parity 11 = multi-drop special mode If with parity or force parity is selected a parity bit is added to the transmitted character and the receiver performs a parity check on incoming data MR1A[4:3] = 11 selects channel A to operate in the special multi-drop mode described in Section 6.3.10 "Multi-drop mode (9-bit or wake-up)".
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MR1A - Mode Register 1 channel A (address 0x0) bit description ...continued Symbol PARITYTYPE Description Channel A parity type select 0 = even 1 = odd This bit selects the parity type (odd or even) if the with parity mode is programmed by MR1A[4:3], and the polarity of the forced parity bit if the force parity mode is programmed. It has no effect if the no parity mode is programmed. In the special multi-drop mode it selects the polarity of the A/D bit.
Table 28. Bit 2
1:0
-
Channel A bits per character select. 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits This field selects the number of data bits per character to be transmitted and received. The character length does not include the start, parity, and stop bits.
7.3.1.3
Mode Register 2 channel A (MR2A)
Table 29. MR2A - Mode Register 2 channel A (address 0x0) bit allocation MR2A is accessed when the channel A MR pointer points to MR2, which occurs after any access to MR1A. Accesses to MR2A do not change the pointer. 7 channel mode 6 5 RTSN Control Tx Table 30. Bit 7 and 6 4 CTSN Enable Tx 3 2 stop bit length 1 0
MR2A - Mode Register 2 channel A (address 0x0) bit description Symbol Description Channel A mode select. Each channel of the DUART can operate in one of the following four modes: 00 = Normal mode (default) 01 = Automatic echo mode 10 = Local loopback mode 11 = Remote loopback mode Table 31 gives a description of the channel modes The user must exercise care when switching into and out of the various modes. The selected mode will be activated immediately upon mode selection, even if this occurs in the middle of a received or transmitted character. Likewise, if a mode is deselected the device will switch out of the mode immediately. An exception to this is switching out of auto echo or remote loopback modes: if the deselection occurs just after the receiver has sampled the stop bit (indicated in auto echo by assertion of RxRDY), and the transmitter is enabled, the transmitter will remain in auto echo mode until the entire stop has been retransmitted.
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MR2A - Mode Register 2 channel A (address 0x0) bit description ...continued Symbol Description Channel A transmitter Request To Send (RTS) control. 0 = No RTS control 1 = RTS control This bit controls the deactivation of the RTSAN output (OP0) by the transmitter. This output is normally asserted by setting OPR[0] and negated by resetting OPR[0]. MR2A[5] = 1 caused OPR[0] to be reset automatically one bit time after the characters in the channel A transmit shift register and in the Tx FIFO, if any, are completely transmitted including the programmed number of stop bits, if the transmitter is not enabled This feature can be used to automatically terminate the transmission of a message as follows (line turnaround): 1. Program auto-reset mode: MR2A[5] = 1 2. Enable transmitter 3. Assert RTSAN: OPR[0] = 1 4. Send message 5. Disable transmitter after the last character is loaded into the channel A Tx FIFO 6. The last character will be transmitted and OPR[0] will be reset one bit time after the last stop bit, causing RTSAN to be negated
Table 30. Bit 5
4
-
Channel A transmitter Clear To Send (CTS) control. 0 = Input CTSAN(IP0) has no effect on the transmitter 1 = CTS control enabled If this bit is a 1, the transmitter checks the state of CTSAN (IP0) each time it is ready to send a character. If IP0 is asserted (LOW), the character is transmitted. If it is negated (HIGH), the TxDA output remains in the marking state and the transmission is delayed until CTSAN goes LOW. Changes in CTSAN while a character is being transmitted do not affect the transmission of that character.
3 to 0
-
Stop bit length select. This field programs the length of the stop bit appended to the transmitted character. Stop bit lengths of 916 to 1 and 1 - 916 to 2 bits, in increments of 116 bit, can be programmed for character lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1 - 116 to 2 stop bits can be programmed in increments of 116 bit. In all cases, the receiver only checks for a mark condition at the center of the stop bit position (one half-bit time after the last data bit, or after the parity bit if enabled is sampled). Refer to Table 32 for the values. If an external 1x clock is used for the transmitter: MR2A[3] = 0 selects one stop bit MR2A[3] = 1 selects two stop bits
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DUART mode description Description The transmitter and receiver operating independently. Places the channel in the automatic echo mode, which automatically retransmits the received data. The following conditions are true while in automatic echo mode: 1. Received data is reclocked and retransmitted on the TxDA output 2. The receive clock is used for the transmitter 3. The receiver must be enabled, but the transmitter need not be enabled 4. The channel A TxRDY and TxEMT status bits are inactive 5. The received parity is checked, but is not regenerated for transmission, i.e. transmitted parity bit is as received 6. Character framing is checked, but the stop bits are retransmitted as received 7. A received break is echoed as received until the next valid start bit is detected 8. CPU to receiver communication continues normally, but the CPU to transmitter link is disabled
Table 31. Mode Normal Automatic echo
Local loopback
Selects local loopback diagnostic mode. In this mode: 1. The transmitter output is internally connected to the receiver input 2. The transmit clock is used for the receiver 3. The TxDA output is held HIGH 4. The RxDA input is ignored 5. The transmitter must be enabled, but the receiver need not be enabled 6. CPU to transmitter and receiver communications continue normally
Remote loopback
Selects remote loopback diagnostic mode. In this mode: 1. Received data is reclocked and retransmitted on the TxDA output 2. The receive clock is used for the transmitter 3. Received data is not sent to the local CPU, and the error status conditions are inactive 4. The received parity is not checked and is not regenerated for transmission, i.e., transmitted parity is as received 5. The receiver must be enabled 6. Character framing is not checked, and the stop bits are retransmitted as received 7. A received break is echoed as received until the next valid start bit is detected
Table 32. 0 1 2 3 4 5 6 7 8 9 A
SC28L92_7
Stop bit length Stop bit length[1] 0.563 0.625 0.688 0.750 0.813 0.875 0.938 1.000 1.563 1.653 1.688
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MR2A[3:0] (hexadecimal)
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Stop bit length ...continued Stop bit length[1] 1.750 1.813 1.875 1.938 2.000
Table 32. B C D E F
[1]
MR2A[3:0] (hexadecimal)
Add 0.5 to values shown for 0 to 7 if channel is programmed for 5 bit per character
7.3.1.4
Mode Register 0 channel B (MR0B) MR0B (address 0x8) is accessed when the channel B MR pointer points to MR1. The pointer is set to MR0 by RESET or by a set pointer command applied via CRB. After reading or writing MR0B, the pointer will point to MR1B. The bit definitions for this register are identical to MR0A, except the FIFO size bit and that all control actions apply to the channel B receiver, transmitter, the corresponding inputs and outputs. MR0B[2:0] are reserved.
7.3.1.5
Mode Register 1 channel B (MR1B) MR1B (address 0x8) is accessed when the channel B MR pointer points to MR1. The pointer is set to MR1 by RESET or by a set pointer command applied via CRB. After reading or writing MR1B, the pointer will point to MR2B. The bit definitions for this register are identical to MR1A, except that all control actions apply to the channel B receiver and transmitter and the corresponding inputs and outputs.
7.3.1.6
Mode Register 2 channel B (MR2B) MR2B (address 0x8) is accessed when the channel B MR pointer points to MR2, which occurs after any access to MR1B. Accesses to MR2B do not change the pointer. The bit definitions for mode register are identical to the bit definitions for MR2A, except that all control actions apply to the channel B receiver and transmitter and the corresponding inputs and outputs.
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7.3.2 Clock select registers
Table 33. 7 CSRA - Clock select register channel A (address 0x1) and CSRB - Clock select register channel B (address 0x9) bit allocation 6 5 4 3 2 1 0 receiver clock select code transmitter clock select code
7.3.2.1
Clock Select Register channel A (CSRA)
Table 34. Bit 7 to 4 CSRA - Clock select register channel A (address 0x1) bit description Description Receiver clock select. The baud rate clock for the channel A receiver is as shown in Table 35, except as follows: 1110 = IP4 - 16x 1111 = IP4 - 1x The receiver clock is always a 16x clock except for CSRA[7:4] = 1111 3 to 0 Transmitter clock select. The baud rate clock for the channel A transmitter is as shown in Table 35, except as follows: 1110 = IP3 - 16x 1111 = IP3 - 1x The transmitter clock is always a 16x clock except for CSRA[3:0] = 1111
Symbol
Table 35. Baud rate (based on a 3.6864 MHz crystal clock) See Table 36 for bit rate characteristics. CSR[7:4] CSR[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 MR0[0] = 0 (Normal mode) ACR[7] = 0 50 110 134.5 200 300 600 1,200 1,050 2,400 4,800 7,200 9,600 38,400 Timer ACR[7] = 1 75 110 134.5 150 300 600 1,200 2,000 2,400 4,800 1,800 9,600 19,200 Timer MR0[0] = 1 (Extended mode I) ACR[7] = 0 300 110 134.5 1200 1800 3600 7200 1,050 14,400 28,800 7,200 57,600 230,400 Timer ACR[7] = 1 450 110 134.5 900 1800 3600 7,200 2,000 14,400 28,800 1,800 57,600 115,200 Timer MR0[2] = 1 (Extended mode II) ACR[7] = 0 4,800 880 1,076 19.200 28.800 57.600 115,200 1,050 57,600 4,800 57,600 9,600 38,400 Timer ACR[7] = 1 7,200 880 1,076 14.400 28.800 57.600 115,200 2,000 57,600 4,800 14,400 9,600 19,200 Timer
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Table 36. Bit rate generator characteristics[1] Crystal or clock = 3.6864 MHz. Normal rate (baud) 50 75 110 134.5 150 200 300 600 1050 1200 1800 2000 2400 4800 7200 9600 19200 38400
[1]
Actual 16x clock (kHz) 0.8 1.2 1.759 2.153 2.4 3.2 4.8 9.6 16.756 19.2 28.8 32.056 38.4 76.8 115.2 153.6 307.2 614.4
Error (%) 0 0 -0.069 0.059 0 0 0 0 -0.260 0 0 0.175 0 0 0 0 0 0
Duty cycle of 16x clock is 50 % 1 %.
7.3.2.2
Clock Select Register channel B (CSRB)
Table 37. Bit 7 to 4 CSRB - Clock select register channel B (address 0x9) bit description Description Receiver clock select. The baud rate clock for the channel B receiver is as shown in Table 35, except as follows: 1110 = IP6 - 16x 1111 = IP6 - 1x The receiver clock is always a 16x clock except for CSRB[7:4] = 1111 3 to 0 Transmitter clock select. The baud rate clock for the channel A transmitter is as shown in Table 35, except as follows: 1110 = IP5 - 16x 1111 = IP5 - 1x The transmitter clock is always a 16x clock except for CSRB[3:0] = 1111
Symbol
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7.3.3 Command registers
Table 38. 7 CRA - Command register channel A (address 0x2) and CRB - Command register channel B (address 0xA) bit allocation 6 5 4 3 disable Tx 2 enable Tx 1 disable Rx 0 enable Rx channel command code
7.3.3.1
Command Register channel A (CRA) CRA is a register used to supply commands to channel A. Multiple commands can be specified in a single write to CRA as long as the commands are non-conflicting, e.g., the enable transmitter and reset transmitter commands cannot be specified in a single command word.
Table 39. Bit 7 to 4 CRA - Command register channel A (address 0x2) bit description Description Miscellaneous commands. Execution of the commands in the upper four bits of this register must be separated by 3 X1 clock edges. Other reads or writes (including writes to the lower four bits) may be inserted to achieve this separation. A description of miscellaneous commands is given in Table 40. Disable channel A transmitter. This command terminates transmitter operation and reset the TxDRY and TxEMT status bits. However, if a character is being transmitted or if a character is in the Tx FIFO when the transmitter is disabled, the transmission of the character(s) is completed before assuming the inactive state. Enable channel A transmitter. Enables operation of the channel A transmitter. The TxRDY and TxEMT status bits will be asserted if the transmitter is idle. Disable channel A receiver. This command terminates operation of the receiver immediately-a character being received will be lost. The command has no effect on the receiver status bits or any other control registers. If the special multi-drop mode is programmed, the receiver operates even if it is disabled. See Section 6.3.10. Enable channel A receiver. Enables operation of the channel A receiver. If not in the special wake-up mode, this also forces the receiver into the search for start-bit state. Miscellaneous commands Description No command. Reset MR pointer. Causes the channel A MR pointer to point to MR1. Reset receiver. Resets the channel A receiver as if a hardware reset had been applied. The receiver is disabled and the FIFO is flushed. Reset transmitter. Resets the channel A transmitter as if a hardware reset had been applied. Reset error status. Clears the channel A received break, parity error, and overrun error bits in the status register (SRA[7:4]). Used in character mode to clear OE status (although RB, PE and FE bits will also be cleared) and in block mode to clear all error status after a block of data has been received. Reset channel A break change interrupt. Causes the channel A break detect change bit in the interrupt status register (ISR[2]) to be cleared to zero.
Symbol
3
-
2 1
-
0
-
Table 40. Command 0000 0001 0010 0011 0100
0101
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Miscellaneous commands ...continued Description Start break. Forces the TxDA output LOW (spacing). If the transmitter is empty the start of the break condition will be delayed up to two bit times. If the transmitter is active the break begins when transmission of the character is completed. If a character is in the Tx FIFO, the start of the break will be delayed until that character, or any other loaded subsequently are transmitted. The transmitter must be enabled for this command to be accepted. Stop break. The TxDA line will go HIGH (marking) within two bit times. TxDA will remain HIGH for one bit time before the next character, if any, is transmitted. Assert RTSN. Causes the RTSN output to be asserted (LOW). Negate RTSN. Causes the RTSN output to be negated (HIGH). Set time-out mode on. The receiver in this channel will restart the C/T as each receive character is transferred from the shift register to the Rx FIFO. The C/T is placed in the counter mode, the start counter or stop counter commands are disabled, the counter is stopped, and the counter ready bit, ISR[3], is reset. (see also watchdog timer description in the receiver Section 6.3.7.) Set MR pointer to 0x0. Disable time-out mode. This command returns control of the C/T to the regular start counter or stop counter commands. It does not stop the counter, or clear any pending interrupts. After disabling the time-out mode, a stop counter command should be issued to force a reset of the ISR[3] bit. Not used. Power-down mode on. In this mode, the DUART oscillator is stopped and all functions requiring this clock are suspended. The execution of commands other than disable Power-down mode (1111) requires a X1/CLK. While in the Power-down mode, do not issue any commands to the CR except the disable Power-down mode command. The contents of all registers will be saved while in this mode. It is recommended that the transmitter and receiver be disabled prior to placing the DUART into Power-down mode. This command is in CRA only. Disable Power-down mode. This command restarts the oscillator. After invoking this command, wait for the oscillator to start up before writing further commands to the CR. This command is in CRA only. For maximum power reduction input pins should be at VSS or VDD.
Table 40. Command 0110
0111 1000 1001 1010
1011 1100
1101 1110
1111
7.3.3.2
Command Register channel B (CRB) CRB is a register used to supply commands to channel B. Multiple commands can be specified in a single write to CRB as long as the commands are non-conflicting, e.g., the enable transmitter and reset transmitter commands cannot be specified in a single command word. The bit definitions for this register are identical to the bit definitions for CRA, with the exception of miscellaneous commands 0xE and 0xF which are used for Power-down mode. These two commands are not used in CRB. All other control actions that apply to CRA also apply to CRB.
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7.3.4 Status registers
7.3.4.1 Status Register channel A (SRA)
Table 41. 7 received break[1]
[1]
SRA - Status register channel A (address 0x1) bit allocation 6 framing error[1] 5 parity error[1] 4 overrun error 3 TxEMTA 2 TxRDYA 1 RxFULLA 0 RxRDYA
These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a reset error status command. In character mode they are discarded when the corresponding data character is read from the FIFO. In block error mode, the error-reset command (command 0x4 or receiver reset) must used to clear block error conditions.
Table 42. Bit 7 -
SRA - Status register channel A (address 0x1) bit description Description Channel A received break. 0 = no 1 = yes This bit indicates that an all zero character of the programmed length has been received without a stop bit. Only a single FIFO position is occupied when a break is received: further entries to the FIFO are inhibited until the RxDA line returns to the marking state for at least one-half a bit time two successive edges of the internal or external 1x clock. This will usually require a HIGH time of one X1 clock period or 3 X1 edges since the clock of the controller is not synchronous to the X1 clock. When this bit is set, the channel A change in break bit in the ISR (ISR[2]) is set. ISR[2] is also set when the end of the break condition, as defined above, is detected. The break detect circuitry can detect breaks that originate in the middle of a received character. However, if a break begins in the middle of a character, it must persist until at least the end of the next character time in order for it to be detected. This bit is reset by command 0x4 (0100) written to the command register or by receiver reset.
Symbol
6
-
Channel A framing error. 0 = no 1 = yes This bit, when set, indicates that a stop bit was not detected (not a logic 1) when the corresponding data character in the FIFO was received. The stop bit check is made in the middle of the first stop bit position.
5
-
Channel A parity error. 0 = no 1 = yes This bit is set when the with parity or force parity mode is programmed and the corresponding character in the FIFO was received with incorrect parity. In the special multi-drop mode the parity error bit stores the receive A/D (Address/Data) bit.
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SRA - Status register channel A (address 0x1) bit description ...continued Description Channel A overrun error. 0 = no 1 = yes This bit, when set, indicates that one or more characters in the received data stream have been lost. It is set upon receipt of a new character when the FIFO is full and a character is already in the receive shift register waiting for an empty FIFO position. When this occurs, the character in the receive shift register (and its break detect, parity error and framing error status, if any) is lost. This bit is cleared by a reset error status command.
Table 42. Bit 4 -
Symbol
3
TxEMTA
Channel A transmitter empty. 0 = no 1 = yes This bit will be set when the transmitter under runs, i.e., both the TxEMT and TxRDY bits are set. This bit and TxRDY are set when the transmitter is first enabled and at any time it is re-enabled after either (a) reset, or (b) the transmitter has assumed the disabled state. It is always set after transmission of the last stop bit of a character if no character is in the Tx Holding Register (TxFIFOA) awaiting transmission. It is reset when the Tx Holding Register (TxFIFOA) is loaded by the CPU, a pending transmitter disable is executed, the transmitter is reset, or the transmitter is disabled while in the under run condition.
2
TxRDYA
Channel A transmitter ready. 0 = no 1 = yes This bit, when set, indicates that the transmit FIFO is not full and ready to be loaded with another character. This bit is cleared when the transmit FIFO is loaded by the CPU and there are (after this load) no more empty locations in the FIFO. It is set when a character is transferred to the transmit shift register. TxRDYA is reset when the transmitter is disabled and is set when the transmitter is first enabled. Characters loaded to the Tx FIFO while this bit is logic 0 will be lost. This bit has different meaning from ISR[0].
1
FFULLA
Channel A FIFO full. 0 = no 1 = yes This bit is set when a character is transferred from the receive shift register to the receive FIFO and the transfer causes the FIFO to become full, i.e., all eight (or 16) FIFO positions are occupied. It is reset when the CPU reads the receive FIFO. If a character is waiting in the receive shift register because the FIFO is full, FFULLA will not be reset when the CPU reads the receive FIFO. This bit has different meaning from ISR1 when MR1[6] is programmed to a logic 1
0
RxRDYA
Channel A receiver ready. 0 = no 1 = yes This bit indicates that a character has been received and is waiting in the FIFO to be read by the CPU. It is set when the character is transferred from the receive shift register to the FIFO and reset when the CPU reads the receive FIFO, only if (after this read) there are no more characters in the FIFO - the Rx FIFO becomes empty.
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7.3.4.2
Status Register channel B (SRB)
Table 43. 7 received break[1]
[1]
SRB - Status register channel B (address 0x9) bit allocation 6 framing error[1] 5 parity error[1] 4 overrun error 3 TxEMTB 2 TxRDYB 1 RxFULLB 0 RxRDYB
These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a reset error status command. In character mode they are discarded when the corresponding data character is read from the FIFO. In block error mode, the error-reset command (command 0x4 or receiver reset) must used to clear block error conditions.
The bit definitions for this register are identical to the bit definitions for SRA, except that all status applies to the channel B receiver and transmitter and the corresponding inputs and outputs.
7.3.5 Output Configuration Control Register (OPCR)
This register controls the signal presented by the OP[7:2] pins. The signal presented by the OP[1:0] pins is controlled by the Rx, Tx, and the command register. The default condition of the OP pins is to drive the complement of the data in the OPR[7:0] register. When OP[7:2] pins drive DMA or interrupt type signals, they switch to open-drain configuration. Otherwise, they drive strong logic 0 or logic 1 levels.
Table 44. 7 configure OP7 Table 45. Bit 7 OPCR - Output configuration control register (address 0xD) bit allocation 6 configure OP6 5 configure OP5 4 configure OP4 3 2 1 0 configure OP3 configure OP2
OPCR - Output configuration control register (address 0xD) bit description Symbol Description OP7 output select 0 = The complement of OPR[7] 1 = The channel B transmitter interrupt output which is the complement of ISR[4]. When in this mode OP7 acts as an open-drain output. Note that this output is not masked by the contents of the IMR.
6
-
OP6 output select 0 = The complement of OPR[6] 1 = The channel A transmitter interrupt output which is the complement of ISR[0]. When in this mode OP6 acts as an open-drain output. Note that this output is not masked by the contents of the IMR.
5
-
OP5 output select 0 = The complement of OPR[5] 1 = The channel B receiver interrupt output which is the complement of ISR[5]. When in this mode OP5 acts as an open-drain output. Note that this output is not masked by the contents of the IMR.
4
-
OP4 output select 0 = The complement of OPR[4] 1 = The channel A receiver interrupt output which is the complement of ISR[1]. When in this mode OP4 acts as an open-drain output. Note that this output is not masked by the contents of the IMR.
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OPCR - Output configuration control register (address 0xD) bit description Symbol Description OP3 output select 00 = The complement of OPR[3] 01 = The counter/timer output, in which case OP3 acts as an open-drain output. In the timer mode, this output is a square wave at the programmed frequency. In the counter mode, the output remains HIGH until terminal count is reached, at which time it goes LOW. The output returns to the HIGH state when the counter is stopped by a stop counter command. Note that this output is not masked by the contents of the IMR. 10 = The 1x clock for the channel B transmitter, which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1x clock is output. 11 = The 1x clock for the channel B receiver, which is the clock that samples the received data. If data is not being received, a free running 1x clock is output.
Table 45. Bit 3 and 2
1 and 0
-
OP2 output select 00 = The complement of OPR[2] 01 = The 16x clock for the channel A transmitter. This is the clock selected by CSRA[3:0], and will be a 1x clock if CSRA[3:0] = 1111. 10 = The 1x clock for the channel A transmitter, which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1x clock is output. 11 = The 1x clock for the channel A receiver, which is the clock that samples the received data. If data is not being received, a free running 1x clock is output.
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7.3.6 Set Output Port bits Register (SOPR)
Ones in the byte written to this register will cause the corresponding bit positions in the OPR to set to 1. Zeros have no effect. This allows software to set individual bits without keeping a copy of the OPR bit configuration.
Table 46. 7 set OP7 Table 47. Bit 7 SOPR - Set output port bits register (address 0xE) bit allocation 6 set OP6 5 set OP5 4 set OP4 3 set OP3 2 set OP2 1 set OP1 0 set OP0
SOPR - Set output port bits register (address 0xE) bit description Description OPR 7 1 = set bit 0 = no change
Symbol
6
-
OPR 6 1 = set bit 0 = no change
5
-
OPR 5 1 = set bit 0 = no change
4
-
OPR 4 1 = set bit 0 = no change
3
-
OPR 3 1 = set bit 0 = no change
2
-
OPR 2 1 = set bit 0 = no change
1
-
OPR 1 1 = set bit 0 = no change
0
-
OPR 0 1 = set bit 0 = no change
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7.3.7 Reset Output Port bits Register (ROPR)
Ones in the byte written to the ROPR will cause the corresponding bit positions in the OPR to set to 0. Zeros have no effect. This allows software to reset individual bits without keeping a copy of the OPR bit configuration.
Table 48. 7 ROPR - Reset output port bits register (address 0xF) bit allocation 6 5 4 3 2 1 0
reset OP7 reset OP6 reset OP5 reset OP4 reset OP3 reset OP2 reset OP1 reset OP0 Table 49. Bit 7 ROPR - Reset output port bits register (address 0xF) bit description Description OPR 7 1 = reset bit 0 = no change 6 OPR 6 1 = reset bit 0 = no change 5 OPR 5 1 = reset bit 0 = no change 4 OPR 4 1 = reset bit 0 = no change 3 OPR 3 1 = set bit 0 = no change 2 OPR 2 1 = reset bit 0 = no change 1 OPR 1 1 = reset bit 0 = no change 0 OPR 0 1 = reset bit 0 = no change
Symbol
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7.3.8 Output Port Register (OPR)
Table 50. OPR - Output port register (no address) bit allocation The output pins (OP pins) drive the complement of the data in this register as controlled by SOPR and ROPR. 7 OP7 Table 51. Bit 7 6 OP6 5 OP5 4 OP4 3 OP3 2 OP2 1 OP1 0 OP0
OPR - Output port register (no address) bit description Description pin OP7 0 = pin HIGH 1 = pin LOW
Symbol
6
-
pin OP6 0 = pin HIGH 1 = pin LOW
5
-
pin OP5 0 = pin HIGH 1 = pin LOW
4
-
pin OP4 0 = pin HIGH 1 = pin LOW
3
-
pin OP3 0 = pin HIGH 1 = pin LOW
2
-
pin OP2 0 = pin HIGH 1 = pin LOW
1
-
pin OP1 0 = pin HIGH 1 = pin LOW
0
-
pin OP0 0 = pin HIGH 1 = pin LOW
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7.3.9 Auxiliary Control Register (ACR)
Table 52. 7 BRG set select ACR - Auxiliary control register (address 0x4) bit allocation 6 5 4 3 2 1 0 counter/timer mode and clock source select enable IP3 enable IP2 enable IP1 enable IP0 COS interrupt COS interrupt COS interrupt COS interrupt
Table 53. Bit 7 -
ACR - Auxiliary control register (address 0x4) bit description Description Baud rate generator set select. This bit selects one of two sets of baud rates to be generated by the BRG (see Table 35). The selected set of rates is available for use by the channel A and B receivers and transmitters as described for CSRA in Table 34 and for CSRB in Table 37. Baud rate generator characteristics are given in Table 36.
Symbol
6 to 4
-
Counter/timer mode and clock source select. This field selects the operating mode of the counter/timer and its clock source as shown in Table 54.
3 to 0
-
IP3, IP2, IP1 and IP0 change-of-state interrupt enable. 0 = off 1 = enabled This field selects which bits of the input port change register (IPCR) cause the input change bit in the interrupt status register (ISR [7]) to be set. If a bit is in the enabled state the setting of the corresponding bit in the IPCR will also result in the setting of ISR [7], which results in the generation of an interrupt output if IMR [7] = 1. If a bit is in the off state, the setting of that bit in the IPCR has no effect on ISR [7].
Table 54. ACR[6:4] 000 001 010 011 100 101 110 111
[1]
ACR[6:4] field definition[1] Mode counter counter counter counter timer timer timer timer Clock source external (IP2) TxCA - 1x clock of channel A transmitter TxCB - 1x clock of channel B transmitter crystal or external clock (X1/CLK) divided by 16 external (IP2) external (IP2) divided by 16 crystal or external clock (X1/CLK) crystal or external clock (X1/CLK) divided by 16
The timer mode generates a square wave.
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7.3.10 Input Port Change Register (IPCR)
Table 55. 7 delta IP3 IPCR - Input port change register (address 0x4) bit allocation 6 delta IP2 5 delta IP1 4 delta IP0 3 state of IP3 2 state of IP2 1 state of IP1 0 state of IP0
Table 56. Bit 7 to 4 -
IPCR - Input port change register (address 0x4) bit description Description IP3, IP2, IP1 and IP0 change of state. 0 = no change 1 = change These bits are set when a change of state, as defined in Section 6.2.9 "Input port", occurs at the respective input pins. They are cleared when the IPCR is read by the CPU. A read of the IPCR also clears ISR[7], the input change bit in the interrupt status register. The setting of these bits can be programmed to generate an interrupt to the CPU.
Symbol
3 to 0
-
IP3, IP2, IP1 and IP0 state. 0 = LOW 1 = HIGH These bits provide the current state of the respective inputs. The information is unlatched and reflects the state of the input pins at the time the IPCR is read.
7.3.11 Interrupt Status Register (ISR)
This register provides the status of all potential interrupt sources. The contents of this register are masked by the Interrupt Mask Register (IMR). If a bit in the ISR is a logic 1 and the corresponding bit in the IMR is also a logic 1, the INTRN output will be asserted (LOW). If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the reading of the ISR. The true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to 0x0 when the DUART is reset.
Table 57. 7 change input port Table 58. Bit 7 ISR - Interrupt status register (address 0x5) bit allocation 6 change break B 5 RxRDYB 4 TxRDYB 3 counter ready 2 change break A 1 RxRDYA 0 TxRDYA
ISR - Interrupt status register (address 0x5) bit description Description Input port change status. 0 = not active 1 = active This bit is a logic 1 when a change of state has occurred at the IP0, IP1, IP2, or IP3 inputs and that event has been selected to cause an interrupt by the programming of ACR[3:0]. The bit is cleared when the CPU reads the IPCR.
Symbol
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ISR - Interrupt status register (address 0x5) bit description ...continued Description Channel B change in break. 0 = not active 1 = active This bit, when set, indicates that the channel B receiver has detected the beginning or the end of a received break. It is reset when the CPU issues a channel B reset break change interrupt command.
Table 58. Bit 6 -
Symbol
5
RxRDYB
RxB interrupt. 0 = not active 1 = active This bit indicates that the channel B receiver is interrupting according to the fill level programmed by the MR0 and MR1 registers or the watchdog timer has timed-out. This bit has a different meaning than the receiver ready/full bit in the status register.
4
TxRDYB
TxB interrupt. 0 = not active 1 = active This bit indicates that the channel B transmitter is interrupting according to the interrupt level programmed in the MR0[5:4] bits. This bit has a different meaning than the TxRDY bit in the status register.
3
-
Counter ready. 0 = not active 1 = active In the counter mode, this bit is set when the counter reaches terminal count and is reset when the counter is stopped by a stop counter command. In the timer mode, this bit is set once each cycle of the generated square wave (every other time that the counter/timer reaches zero count). The bit is reset by a stop counter command. The command, however, does not stop the counter/timer.
2
-
Channel A change in break. 0 = not active 1 = active This bit, when set, indicates that the channel A receiver has detected the beginning or the end of a received break. It is reset when the CPU issues a channel A reset break change interrupt command.
1
RxRDYA
RxA interrupt. 0 = not active 1 = active This bit indicates that the channel A receiver is interrupting according to the fill level programmed by the MR0 and MR1 registers or the watchdog timer has timed-out. This bit has a different meaning than the receiver ready/full bit in the status register.
0
TxRDYA
TxA interrupt. 0 = not active 1 = active This bit indicates that the channel A transmitter is interrupting according to the interrupt level programmed in the MR0[5:4] bits. This bit has a different meaning than the TxRDY bit in the status register.
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7.3.12 Interrupt Mask Register (IMR)
The programming of this register selects which bits in the ISR causes an interrupt output. If a bit in the ISR is a logic 1 and the corresponding bit in the IMR is also a logic 1 the INTRN output will be asserted. If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the programmable interrupt outputs OP3 to OP7 or the reading of the ISR.
Table 59. 7 input port change Table 60. Bit 7 IMR - Interrupt mask register (address 0x5) bit allocation 6 change break B 5 RxRDYB FFULLB 4 TxRDYB 3 counter ready 2 change break A 1 RxRDYA FFULLA 0 TxRDYA
IMR - Interrupt mask register (address 0x5) bit description Description Input port change. 0 = not enabled 1 = enabled
Symbol
6
-
Channel B change in break. 0 = not enabled 1 = enabled
5
RxRDYB FFULLB
RxB interrupt. 0 = not enabled 1 = enabled TxB interrupt. 0 = not enabled 1 = enabled
4
TxRDYB
3
-
Counter ready. 0 = not enabled 1 = enabled
2
-
Channel A change in break. 0 = not enabled 1 = enabled
1
RxRDYA FFULLA
RxA interrupt. 0 = not enabled 1 = enabled TxA interrupt. 0 = not enabled 1 = enabled
0
TxRDYA
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7.3.13 Interrupt Vector Register (IVR; 68xxx mode) or General Purpose register (GP; 80xxx mode)
This register stores the Interrupt Vector. It is initialized to 0x0F on hardware reset and is usually changed from this value during initialization of the SC28L92. The contents of this register will be placed on the data bus when IACKN is asserted LOW or a read of address 0xC is performed. When not operating in the 68xxx mode, this register may be used as a general purpose one byte storage register. A convenient use could be to store a shadow of the contents of another SC28L92 register (IMR, for example).
Table 61. 7 IVR/GP - Interrupt vector register or general purpose register (address 0xC) bit allocation 6 5 4 3 2 1 0 interrupt vector (68xxx mode) or one byte storage (80xxx mode)
7.3.14 Counter/timer registers
Table 62. Bit 7:0 CTPU - Counter/Timer Preset Upper register (address 0x6) bit description Description The upper eight (8) bits for the 16-bit counter/timer preset register CTPL - Counter/Timer preset Lower register (address 0x7) bit description Description The lower eight (8) bits for the 16-bit counter/timer preset register Symbol
Table 63. Bit 7:0 -
Symbol
The CTPU and CTPL hold the eight MSBs and eight LSBs, respectively, of the value to be used by the counter/timer in either the counter or timer modes of operation. The minimum value which may be loaded into the CTPU/CTPL registers is 0x0002. Note that these registers are write only and cannot be read by the CPU. In the timer mode, the C/T generates a square wave whose period is twice the value (in C/T clock periods) of the CTPU and CTPL. The waveform so generated is often used for a data clock. The formula for calculating the divisor n to load to the CTPU and CTPL for a particular 1x data clock is shown in Equation 2. counter/timer clock frequency n = ---------------------------------------------------------------------------------2 x 16 x ( desired baud rate ) (2)
Often this division will result in a non-integer number; 26.3, for example. One can only program integer numbers in a digital divider. Therefore, 26 would be chosen. This gives a baud rate error of 0.3/26.3 which is 1.14 %; well within the ability asynchronous mode of operation. The C/T will not be running until it receives an initial start counter command (read at address A3 to A0 = 1110). After this, while in timer mode, the C/T will run continuously. Receipt of a start counter command (read with A3 to A0 = 1110) causes the counter to terminate the current timing cycle and to begin a new cycle using the values in CTPU and CTPL. If the value in CTPU and CTPL is changed, the current half-period will not be affected, but subsequent half periods will be affected.
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The counter ready status bit (ISR[3]) is set once each cycle of the square wave. The bit is reset by a stop counter command (read with A3 to A0 = 1111). The command however, does not stop the C/T. The generated square wave is output on OP3 if it is programmed to be the C/T output. In the counter mode, the value C/T loaded into CTPU and CTPL by the CPU is counted down to 0. Counting begins upon receipt of a start counter command. Upon reaching terminal count 0x0000, the counter ready interrupt bit (ISR[3]) is set. The counter continues counting past the terminal count until stopped by the CPU. If OP3 is programmed to be the output of the C/T, the output remains HIGH until terminal count is reached, at which time it goes LOW. The output returns to the HIGH state and ISR[3] is cleared when the counter is stopped by a stop counter command. The CPU may change the values of CTPU and CTPL at any time, but the new count becomes effective only on the next start counter commands. If new values have not been loaded, the previous count values are preserved and used for the next count cycle. In the counter mode, the current value of the upper and lower 8 bits of the counter (CTU, CTL) may be read by the CPU. It is recommended that the counter be stopped when reading to prevent potential problems which may occur if a carry from the lower 8 bits to the upper 8 bits occurs between the times that both halves of the counter are read. However, note that a subsequent start counter command will cause the counter to begin a new count cycle using the values in CTPU and CTPL. When the C/T clock divided by 16 is selected, the maximum divisor becomes 1,048,575.
7.4 Output port notes
The output ports are controlled from four places: the OPCR register, the OPR register, the MR registers and the command register (except the SCC2681 and SCC68681). The OPCR register controls the source of the data for the output ports OP2 to OP7. The data source for output ports OP0 and OP1 is controlled by the MR and CR registers. When the OPR is the source of the data for the output ports, the data at the ports is inverted from that in the OPR register. The content of the OPR register is controlled by the Set Output Port bits command and the Reset Output Port bits command. These commands are at 0xE and 0xF, respectively. When these commands are used, action takes place only at the bit locations where ones exist. For example, a logic 1 in bit location 5 of the data word used with the Set Output Port bits command will result in OPR5 being set to one. The OP5 would then be set to logic 0 (VSS). Similarly, a logic 1 in bit position 5 of the data word associated with the Reset Output Ports bits command would set OPR5 to logic 0 and, hence, the pin OP5 to a logic 1 (VDD).
7.5 The CTS, RTS, CTS enable Tx signals
Clear To Send (CTS) is usually meant to be a signal to the transmitter meaning that it may transmit data to the receiver. The CTS input is on pin IP0 for TxA and on IP1 for TxB. The CTS signal is active LOW; thus, it is called CTSAN for TxA and CTSBN for TxB. RTS is usually meant to be a signal from the receiver indicating that the receiver is ready to receive data. It is also active LOW and is, thus, called RTSAN for RxA and RTSBN for RxB. RTSAN is on pin OP0 and RTSBN is on OP1. A receiver's RTS output will usually be connected to the CTS input of the associated transmitter. Therefore, one could say that RTS and CTS are different ends of the same wire.
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Product data sheet
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SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
MR2[4] is the bit that allows the transmitter to be controlled by the CTS pin (IP0 or IP1). When this bit is set to one AND the CTS input is driven HIGH, the transmitter will stop sending data at the end of the present character being serialized. It is usually the RTS output of the receiver that will be connected to the transmitter's CTS input. The receiver will set RTS HIGH when the receiver FIFO is full AND the start bit of the 9th or 17th character is sensed. Transmission then stops with 9 or 17 valid characters in the receiver. When MR2[4] is set to one, CTSN must be at zero for the transmitter to operate. If MR2[4] is set to zero, the IP pin will have no effect on the operation of the transmitter. MR1[7] is the bit that allows the receiver to control OP0. When OP0 (or OP1) is controlled by the receiver, the meaning of that pin will be.
8. Limiting values
Table 64. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Tamb Tstg VCC VS PD ambient temperature storage temperature voltage from VCC to GND voltage from any pin to GND package power dissipation PLCC44 QFP44 HVQFN48 Pder dissipation derating factor PLCC44 QFP44 HVQFN48
[1] [2] [3]
[3] [3]
Conditions
[1][2]
Min -40 -65 -0.5 -0.5 -
Max +85 +150 +7.0
Unit C C V
VCC + 0.5 V 2.4 1.78 0.5 19 14 28 W W W mW/C mW/C mW/C
above 25 C -
For operation at elevated temperatures, the device must be derated based on 150 C maximum junction temperature. Parameters are valid over specified temperature range. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
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Product data sheet
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SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
9. Static characteristics
Table 65. Static characteristics, 5 V operation[1] VCC = 5 V 10 %; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VIL VIH VOL VOH II(1XPD) IIL(X1) IIH(X1) II Parameter input LOW voltage input HIGH voltage output LOW voltage output HIGH voltage except pin X1/CLK pin X1/CLK IOL = 2.4 mA except open-drain outputs; IOH = -400 A
[2]
Conditions
Min 2.4 0.8VCC -
Typ 1.5 2.4 0.2
Max 0.8 0.4 0.5 0 130
Unit V V V V V A A A
VCC - 0.5 0.5 -130 0 0.05 -
Power-down mode input current VI = 0 V to VCC on pin X1/CLK operating input LOW current on pin X1/CLK VI = 0 V
operating input HIGH current on VI = VCC pin X1/CLK input leakage current VI = 0 V to VCC all except input port pins input port pins
[3]
-0.5 -8 -0.5 -0.5 [4]
+0.05 +0.05 -
+0.5 +0.5 0.5 0.5
A A A A A A
IOZH IOZL IODL IODH ICC
output off current HIGH, 3-state data bus output off current LOW, 3-state data bus open-drain output LOW current in off state open-drain output HIGH current in off state power supply current
VI = VCC VI = 0 V VI = 0 V VI = VCC CMOS input levels operating mode Power-down mode
-
7 1
25 5
mA A
[1]
The following conditions apply: a) Parameters are valid over specified temperature and voltage range. b) All voltage measurements are referenced to ground. For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of 5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8VCC. All time measurements are referenced at input voltages of 0.8 V and 2.0 V, and output voltages of 0.8 V and 2.0 V, as appropriate. c) Typical values are at 25 C, typical supply voltages, and typical processing parameters. Test conditions for outputs: CL = 125 pF, except open-drain outputs. Test conditions for open-drain outputs: CL = 125 pF, constant current source = 2.6 mA. Input port pins have active pull-up transistors that will source a typical 2 A from VCC when the input pins are at VSS. Input port pins at VCC source 0.0 A. All outputs are disconnected. Inputs are switching between CMOS levels of VCC - 0.2 V and VSS + 0.2 V.
[2] [3] [4]
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Product data sheet
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NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
60 tDD (ns)
(1)
001aae302
40
(2)
20 12 pF 30 pF 100 pF 125 pF 230 pF
0 0 40 80 120 160 200 CL (pF) 240
(1) VCC = 3.3 V; Tamb = 25 C (2) VCC = 5.0 V; Tamb = 25 C Bus cycle times: 80xxx mode: tDD + tRWD = 70 ns for VCC = 5 V or 40 ns for VCC = 3.3 V + rise and fall time of control signals. 68xxx mode: tCSC + tDAT + 1 cycle of the X1 clock for = 70 ns for VCC = 5 V + rise and fall time of control signals.
Fig 9. Port timing as a function of capacitive loading at typical conditions
SC28L92_7
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Product data sheet
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52 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 66. Static characteristics, 3.3 V operation[1] VCC = 3.3 V 10 %; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VIL VIH VOL VOH II(1XPD) IIL(X1) IIH(X1) II Parameter input LOW voltage input HIGH voltage output LOW voltage output HIGH voltage Power-down mode input current on pin X1/CLK operating input LOW current on pin X1/CLK operating input HIGH current on pin X1/CLK input leakage current IOL = 2.4 mA except open-drain outputs; IOH = -400 A VI = 0 V to VCC VI = 0 V VI = VCC VI = 0 V to VCC all except input port pins input port pins IOZH IOZL IODL IODH ICC output off current HIGH, 3-state data bus VI = VCC
[3] [3] [2]
Conditions
Min 0.8VCC -
Typ 0.65 1.7 0.2
Max 0.4
Unit V V V A A A
0.2VCC V
VCC - 0.5 VCC - 0.2 -0.5 -80 0 +0.05 +0.5 0 80
-0.5 -8 -0.5 -0.5 -
+0.05 +0.5 -
+0.5 +0.5 0.5 0.5
A A A A A A
output off current LOW, 3-state VI = 0 V data bus open-drain output LOW current VI = 0 V in off state open-drain output HIGH current in off state power supply current VI = VCC CMOS input levels operating mode Power-down mode
[4]
-
1
5 5.0
mA A
[1]
The following conditions apply: a) Parameters are valid over specified temperature and voltage range. b) All voltage measurements are referenced to ground. For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of 5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8VCC. All time measurements are referenced at input voltages of 0.8 V and 2.0 V, and output voltages of 0.8 V and 2.0 V, as appropriate. c) Typical values are at 25 C, typical supply voltages, and typical processing parameters. Test conditions for outputs: CL = 125 pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 125 pF, constant current source = 2.6 mA. Input port pins have active pull-up transistors that will source a typical 2 A from VCC when they are at VSS. Input port pins at VCC source 0.0 A. All outputs are disconnected. Inputs are switching between CMOS levels of VCC - 0.2 V and VSS + 0.2 V.
[2] [3] [4]
SC28L92_7
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Product data sheet
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53 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
10. Dynamic characteristics
Table 67. Dynamic characteristics, 5 V operation[1] VCC = 5.0 V 10 %, Tamb = -40 C to +85 C, unless otherwise specified. Symbol tRES tAS tAH tCS tCH tRW tDD tDA tDF tDI tDS tDH tRWD Parameter reset pulse width A0 to A3 set-up time to RDN, WRN LOW A0 to A3 hold time from RDN, WRN LOW CEN set-up time to RDN, WRN LOW CEN hold time from RDN, WRN LOW WRN, RDN pulse width (LOW time) data valid after RDN LOW RDN LOW to data bus active data bus floating after RDN or CEN HIGH RDN or CEN HIGH to data bus invalid data bus set-up time before WRN or CEN HIGH (write cycle) data hold time after WRN HIGH HIGH time between read and/or write cycles port in set-up time before RDN LOW (Read IP ports cycle) port in hold time after RDN HIGH OP port valid after WRN or CEN HIGH (OPR write cycle) INTRN (or OP3 to OP7 when used as interrupts) read Rx FIFO (RxRDY/FFULL interrupt) write Tx FIFO (TxRDY interrupt) reset command (delta break change interrupt) stop C/T command (counter/timer interrupt read IPCR (delta input port change interrupt) write IMR (clear of change interrupt mask bit(s))
[2][4] [4]
Conditions
Min 100 10 20 0 0 15
Typ 18 6 12 8 40 17 -12 10
Max 55 20 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Reset timing (see Figure 10) Bus timing[2] (see Figure 11)
125 pF load; see Figure 9 for smaller loads
[3]
0 0 25 0 17
Port timing[2] (see Figure 15) tPS tPH tPD 0 0 -20 -20 40 60 ns ns ns
Interrupt timing (see Figure 16) tIR 40 40 40 40 40 40 60 60 60 60 60 60 ns ns ns ns ns ns
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Product data sheet
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NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 67. Dynamic characteristics, 5 V operation[1] ...continued VCC = 5.0 V 10 %, Tamb = -40 C to +85 C, unless otherwise specified. Symbol tCLK fCLK tCTC fCTC tRX fRX tTX fTX Parameter X1/CLK HIGH or LOW time X1/CLK frequency C/T clock (IP2) HIGH or LOW time (C/T external clock input) C/T clock (IP2) frequency RxC HIGH or LOW time RxC frequency TxC HIGH or LOW time TxC frequency 16x 16x 1x 16x 16x 1x Transmitter timing, external clock (see Figure 18) tTXD tTCS TxD output delay from TxC LOW (TxC input pin) output delay from TxC output pin LOW to TxD data output RxD data set-up time to RxC HIGH RxD data hold time from RxC HIGH DACKN LOW (read cycle) from X1 HIGH DACKN LOW (write cycle) from X1 HIGH DACKN high-impedance from CEN or IACKN HIGH CEN or IACKN set-up time to X1 HIGH for minimum DACKN cycle
[7] [5][6] [5][6] [5] [5]
Conditions
Min 30 0.1 30 0 30 0 0 30 0 -
Typ 20 3.686 10 10 10 40 6
Max 8 8 16 1 16 1 60 30
Unit ns MHz ns MHz ns MHz MHz ns MHz MHz ns ns
Clock timing (see Figure 17)
Receiver timing, external clock (see Figure 19) tRXS tRXH tDCR tDCW tDAT tCSC 50 50 16 40 40 15 15 8 8 35 35 10 ns ns ns ns ns ns
68xxx or Motorola bus timing (see Figure 12, 13 and 14)[7]
[1]
The following conditions apply: a) Parameters are valid over specified temperature and voltage range. b) All voltage measurements are referenced to ground. For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of 5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8VCC. All time measurements are referenced at input voltages of 0.8 V and 2.0 V, and output voltages of 0.8 V and 2.0 V, as appropriate. c) Test conditions for outputs: CL = 125 pF, except open-drain outputs. Test conditions for open-drain outputs: CL = 125 pF, constant current source = 2.6 mA. d) Typical values are the average values at +25 C and 5 V. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the strobing input. CEN and RDN (also CEN and WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle. Guaranteed by characterization of sample units. If CEN is used as the strobing input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must be negated for tRWD to guarantee that any status register changes are valid. Minimum frequencies are not tested but are guaranteed by design. Clocks for 1x mode should maintain a 60/40 duty cycle or better.
[2] [3] [4] [5] [6]
SC28L92_7
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Product data sheet
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55 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
[7]
Minimum DACKN time is ((tDCR or tDCW) tCSC + 2 X1 edges + rise time over 5 ns). Two X1 edges is 273 ns at 3.6864 MHz. For faster bus cycles, the 80xxx bus timing may be used while in the 68xxx mode. It is not necessary to wait for DACKN to insure the proper operation of the SC26C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the bus cycle. DACKN LOW or CEN HIGH completes the write cycle.
Table 68. Dynamic characteristics, 3.3 V operation[1] VCC = 3.3 V 10 %, Tamb = -40 C to +85 C, unless otherwise specified. Symbol tRES Bus tAS tAH tCS tCH tRW tDD tDA tDF tDI tDS tDH tRWD Parameter reset pulse width timing[2] (see Figure 11) 10 33 0 0 20 125 pF load; see Figure 9 for smaller loads
[3]
Conditions
Min 100
Typ 20 6 16 10 46 15 20 -15 10
Max 75 20 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Reset timing (see Figure 10)
A0 to A3 set-up time to RDN, WRN LOW A0 to A3 hold time from RDN, WRN LOW CEN set-up time to RDN, WRN LOW CEN hold time from RDN, WRN LOW WRN, RDN pulse width (LOW time) data valid after RDN LOW RDN LOW to data bus active data bus floating after RDN or CEN HIGH RDN or CEN HIGH to data bus invalid data bus set-up time before WRN or CEN HIGH (write cycle) data hold time after WRN HIGH HIGH time between read and/or write cycles port in set-up time before RDN LOW (Read IP ports cycle) port in hold time after RDN HIGH OP port valid after WRN or CEN HIGH (OPR write cycle) INTRN (or OP3 to OP7 when used as interrupts) read Rx FIFO (RxRDY/FFULL interrupt) write Tx FIFO (TxRDY interrupt) reset command (delta break change interrupt) stop C/T command (counter/timer interrupt read IPCR (delta input port change interrupt) write IMR (clear of change interrupt mask bit(s))
[2][4] [4]
0 0 43 0 27
Port timing[2] (see Figure 15) tPS tPH tPD 0 0 -20 -20 50 75 ns ns ns
Interrupt timing (see Figure 16) tIR 40 40 40 40 40 40 79 79 79 79 79 79 ns ns ns ns ns ns
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Product data sheet
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SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 68. Dynamic characteristics, 3.3 V operation[1] ...continued VCC = 3.3 V 10 %, Tamb = -40 C to +85 C, unless otherwise specified. Symbol tCLK fCLK tCTC fCTC tRX fRX tTX fTX Parameter X1/CLK HIGH or LOW time X1/CLK frequency C/T clock (IP2) HIGH or LOW time (C/T external clock input) C/T clock (IP2) frequency RxC HIGH or LOW time RxC frequency TxC HIGH or LOW time TxC frequency 16x 16x 1x 16x 16x 1x Transmitter timing, external clock (see Figure 18) tTXD tTCS TxD output delay from TxC LOW (TxC input pin) output delay from TxC output pin LOW to TxD data output RxD data set-up time to RxC HIGH RxD data hold time from RxC HIGH DACKN LOW (read cycle) from X1 HIGH DACKN LOW (write cycle) from X1 HIGH DACKN high-impedance from CEN or IACKN HIGH CEN or IACKN set-up time to X1 HIGH for minimum DACKN cycle
[7] [5][6] [5][6] [5] [5]
Conditions
Min 35 0.1 30 0 30 0 0 30 0 -
Typ 25 3.686 15 10 15 40 8
Max 8 8 16 1 16 1 78 30
Unit ns MHz ns MHz ns MHz MHz ns MHz MHz ns ns
Clock timing (see Figure 17)
Receiver timing, external clock (see Figure 19) tRXS tRXH tDCR tDCW tDAT tCSC 50 50 30 10 10 18 18 10 10 57 57 15 ns ns ns ns ns ns
68xxx or Motorola bus timing (see Figure 12, 13 and 14)[7]
[1]
The following conditions apply: a) Parameters are valid over specified temperature and voltage range. b) All voltage measurements are referenced to ground. For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of 5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8VCC. All time measurements are referenced at input voltages of 0.8 V and 2.0 V, and output voltages of 0.8 V and 2.0 V, as appropriate. c) Test conditions for outputs: CL = 125 pF, except open-drain outputs. Test conditions for open-drain outputs: CL = 125 pF, constant current source = 2.6 mA. d) Typical values are the average values at +25 C and 3.3 V. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the strobing input. CEN and RDN (also CEN and WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle. Guaranteed by characterization of sample units. If CEN is used as the strobing input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must be negated for tRWD to guarantee that any status register changes are valid. Minimum frequencies are not tested but are guaranteed by design. Clocks for 1x mode should maintain a 60/40 duty cycle or better.
[2] [3] [4] [5] [6]
SC28L92_7
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Product data sheet
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NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
[7]
Minimum DACKN time is ((tDCR or tDCW) tCSC + 2 X1 edges + rise time over 5 ns). Two X1 edges is 273 ns at 3.6864 MHz. For faster bus cycles, the 80xxx bus timing may be used while in the 68xxx mode. It is not necessary to wait for DACKN to insure the proper operation of the SC26C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the bus cycle. DACKN LOW or CEN HIGH completes the write cycle.
11. Timing diagrams
tRES RESET RESETN tRES
001aae303 001aae304
a. 80xxx mode Fig 10. Reset timing
b. 68xxx mode
A0 to A3 tAS CEN tCS tCS RDN tDD D0 to D7 (read) float not valid valid tDF float tRWD WDN tDS tDH D0 to D7 (write) valid
001aae305
tAH
tRW
tRWD
Fig 11. Bus timing (80xxx mode)
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Product data sheet
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SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
tCSC X1/CLK tAS A0 to A3 tCS R/WN tAH CEN tDD D0 to D7 tDA DACKN tDCR tDAT not valid data valid tDAH tDF tRWD tCH
001aae306
DACKN LOW requires two rising edges of X1 clock after CEN is LOW.
Fig 12. Bus timing, read cycle (68xxx mode)
tCSC X1/CLK tAS A0 to A3 tCS R/WN tAH CEN tDS D0 to D7 tDAH DACKN tDCW tDAT
001aae308
tCH
tRWD
tDH
DACKN LOW requires two rising edges of X1 clock after CEN is LOW.
Fig 13. Bus timing, write cycle (68xxx mode)
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Product data sheet
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SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
tCSC X1/CLK
INTRN
IACKN tDD D0 to D7 tDCR DACKN tDAL tCSD tDAT
001aae309
tDF
tDAH
DACKN LOW requires two rising edges of X1 clock after CEN is LOW.
Fig 14. Interrupt cycle timing (68xxx mode)
RDN tPS IP0 to IP6
001aae311
tPH
a. Input pins.
WRN tPD OP0 to OP6 old data new data
001aae312
b. Output pins. Fig 15. Port timing
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Product data sheet
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SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
WRN
VM
tIR interrupt output(1) VOL + 0.5 V VOL
RDN
VM
tIR interrupt output(1) VOL + 0.5 V VOL
001aae313
The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching signal, VM, to a point 0.2 V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment are pronounced and can greatly affect the resultant measurement. (1) IRQN or OP3 to OP7 when used as interrupt outputs.
Fig 16. Interrupt timing (80xxx mode)
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SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
X1/CLK C/T clock RxC TxC
tCLK tCTC tRX tTX CLK tCLK tCTC tRX tTX
3 pF parasitic capacitance
VCC resistor required for TTL input
470
X1
X2 (must be left open)
X1
2 pF
SC28L92
C1
3.6864 MHz
50 k to 100 k
C2 4 pF
X2
3 pF parasitic capacitance
to UART circuit
001aae314
C1 = C2 24 pF for CL = 13.5 pF. For the oscillator feedback loop, the capacitors C1 and C2 are in series. C1 and C2 should be chosen according to the crystal manufacturer's specification. C1 and C2 values will include any parasitic capacitance of the wiring and X1, X2 pins. Package capacitance approximately 4 pF.
Fig 17. Clock timing
1 bit time (1 or 16 clocks) TxC (input) tTXD TxD tTCS TxC (1x output)
001aae315
Fig 18. Transmitter external clocks
RxC (1x input) tRXS RxD
001aae316
tRXH
Fig 19. Receiver external clock
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Product data sheet
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SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
TxD transmitter enabled TxRDY (SR2) WRN D1 CTSN(1) (IP0) RTSN(2) (OP0)
D1
D2
D3
break
D4
D6
D8
D9
start break
D10
stop break
D11 will not be written to the TxFIFO
D12
OPR(0) = 1
OPR(0) = 1
001aae317
(1) Timing shown for MR2[4] = 1. (2) Timing shown for MR2[5] = 1.
Fig 20. Transmitter timing
RxD receiver enabled RxRDY (SR) FFULL (CR) RxRDY/ FFULL (OP5)(2) RDN
D1
D2
D8
D9
D10
D11
D12
D13
D12, D13 will be lost due to receiver disable
status data OVERRUN (SR) RTS(1) (OP0) OPR[0] = 1 D1 D11 will be lost due to overrun
status data D2
status data D3
status data D10 reset by command
001aae318
(1) Timing shown for MR1[7] = 1. (2) Shown for OPCR[4] = 1 and MR[6] = 0.
Fig 21. Receiver timing
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Product data sheet
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SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
master station: TxD
bit 9 ADD#1 1 D0
bit 9 0
bit 9 ADD#2 1
transmitter enabled TxRDY (SR) WRN MR1[4:3] = 11 ADD#1 D0 MR1[2] = 0 MR1[2] = 1 ADD#2 MR1[2] = 1
peripheral station: RxD receiver enabled RxRDY (SR) RDN/WRN MR1[4:3] = 11
bit 9 0
bit 9 ADD#1 1 D0
bit 9 0
bit 9 ADD#2 1
bit 9 0
ADD#1
status data D0
status data ADD#2
001aae319
Fig 22. Wake-up mode timing
12. Test information
I = 2.4 mA
INTRN DACKN
125 pF
+5 V
D0 to D7 TxDA/TxDB OP0 to OP7
125 pF
I = 2.4 mA VOL return to VCC for a 0 level I = 400 A VOH return to VSS for a 1 level
001aae320
Fig 23. Test conditions on outputs
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Product data sheet
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NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
13. Package outline
PLCC44: plastic leaded chip carrier; 44 leads SOT187-2
eD y X A ZE
eE
39
29 28
bp
40
b1 wM 44 HE A e A4 A1 (A 3) k 7 e D HD 17 ZD B vMB vM A 6 18 Lp detail X
1
pin 1 index
E
0
5 scale
10 mm
DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 e UNIT A A3 D(1) E(1) eD eE HD bp b1 max. min.
mm inches 4.57 4.19 0.51 0.25 0.01 3.05 0.12 0.53 0.33 0.81 0.66
HE
k
Lp
1.44 1.02
v
0.18
w
0.18
y
0.1
ZD(1) ZE(1) max. max.
2.16 2.16
16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.63 0.59 0.63 0.59
45 o
0.180 0.02 0.165
0.021 0.032 0.656 0.656 0.05 0.013 0.026 0.650 0.650
0.695 0.695 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.685 0.685 0.042 0.040
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT187-2 REFERENCES IEC 112E10 JEDEC MS-018 JEITA EDR-7319 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 01-11-14
Fig 24. Package outline SOT187-2 (PLCC44)
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Product data sheet
Rev. 07 -- 19 December 2007
65 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vM A 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.1 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.4 0.2 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 97-08-01 03-02-25
Fig 25. Package outline SOT307-2 (QFP44)
SC28L92_7 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 -- 19 December 2007
66 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 6 x 6 x 0.85 mm
D B A
SOT778-4
terminal 1 index area
E
A A1 c
detail X
C e1 e
13
1/2 e
b
24 25
v w
M M
CAB C
y1 C
y
L
12
e
Eh 1/2 e
e2
1 36
terminal 1 index area
48
37
X 0 2.5 scale 5 mm
Dh
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 1 A1 0.05 0.00 b 0.25 0.15 c 0.2 D(1) 6.1 5.9 Dh 4.75 4.45 E(1) 6.1 5.9 Eh 4.75 4.45 e 0.4 e1 4.4 e2 4.4 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included OUTLINE VERSION SOT778-4 REFERENCES IEC --JEDEC --JEITA --EUROPEAN PROJECTION ISSUE DATE 04-07-30 04-10-07
Fig 26. Package outline SOT778-4 (HVQFN48)
SC28L92_7 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 -- 19 December 2007
67 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
14. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
SC28L92_7 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 -- 19 December 2007
68 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
14.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 27) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 69 and 70
Table 69. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 70. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 27.
SC28L92_7
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 -- 19 December 2007
69 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 27. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
15. Abbreviations
Table 71. Acronym DMA UART FIFO CPU COS BRG MIDI C/T Abbreviations Description Direct Memory Access Universal Asynchronous Receiver/Transmitter First In/First Out Central Processing Unit Change Of State Baud Rate Generator Musical Instrument Digital Interface Counter/Timer
SC28L92_7
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 -- 19 December 2007
70 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
16. Revision history
Table 72. Revision history Release date 20071219 Data sheet status Product data sheet Change notice Supersedes SC28L92_6 Document ID SC28L92_7 Modifications:
* * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. added HVQFN48 package option Figure 1 "Block diagram (80xxx mode)" modified: - reversed position of "control" and "timing" notations - reversed direction of signals IP0 to IP6
*
Figure 2 "Block diagram (68xxx mode)" modified: - corrected pin name from "RDN" to "R/WN" - corrected pin name from "WRN" to "IACKN" - corrected pin name from "RESET" to "RESETN" - added signal DACKN - reversed position of "control" and "timing" notations - reversed direction of signals IP0 to IP5
*
Section 6.1.4 "FIFO configuration": - 1st paragraph, 4th sentence: changed "MR0[3] bit" to "MR0A[3] bit" - 1st paragraph, added new 6th sentence - 2nd paragraph: changed "MR0[3] bit" to "MR0A[3] bit"
*
Table 24 "MR0A - Mode Register 0 channel A (address 0x0) bit description": - description for bit 3: added "for channel A and channel B" - description for bits [2:0]: in last line of description, changed "MR2[2:0]" to "MR0[2:0]"
*
Table 25: - added Table note 1 - removed "(default)" (2 places)
*
Table 26: - added Table note 1 - removed "(default)" (2 places)
* *
SC28L92_6 SC28L92_5 (9397 750 13125) SC28L92_4 (9397 750 06796) SC28L92_3 (9397 750 05979) SC28L92_2 (9397 750 04465) SC28L92_1
Section 7.3.1.4 "Mode Register 0 channel B (MR0B)", 2nd paragraph re-written. Table 64 "Limiting values": added specifications for HVQFN48 package Product data sheet Product specification Product specification Product specification Preliminary specification SC28L92_5 (9397 750 13125) SC28L92_4 (9397 750 06796) SC28L92_3 (9397 750 05979) SC28L92_2 (9397 750 04465) SC28L92_1 -
20060426 20040907 20000121 19990507 19981005 -
SC28L92_7
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 -- 19 December 2007
71 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
SC28L92_7
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 -- 19 December 2007
72 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
19. Contents
1 2 3 4 5 5.1 5.2 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 7 7.1 7.2 7.3 7.3.1 7.3.1.1 7.3.1.2 7.3.1.3 7.3.1.4 7.3.1.5 7.3.1.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional description . . . . . . . . . . . . . . . . . . 13 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data bus buffer . . . . . . . . . . . . . . . . . . . . . . . . 13 Operation control . . . . . . . . . . . . . . . . . . . . . . 13 Interrupt control . . . . . . . . . . . . . . . . . . . . . . . 13 FIFO configuration . . . . . . . . . . . . . . . . . . . . . 14 68xxx mode . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timing circuits. . . . . . . . . . . . . . . . . . . . . . . . . 14 Crystal clock . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Baud rate generator . . . . . . . . . . . . . . . . . . . . 15 Counter/timer . . . . . . . . . . . . . . . . . . . . . . . . . 15 Timer mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . 16 Time-out mode . . . . . . . . . . . . . . . . . . . . . . . . 16 Time-out mode caution . . . . . . . . . . . . . . . . . . 17 Communications channels A and B . . . . . . . . 17 Input port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Output port . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Transmitter reset and disable . . . . . . . . . . . . . 19 Receiver FIFO . . . . . . . . . . . . . . . . . . . . . . . . 20 Receiver status bits . . . . . . . . . . . . . . . . . . . . 20 Receiver reset and disable . . . . . . . . . . . . . . . 20 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Receiver time-out mode . . . . . . . . . . . . . . . . . 21 Time-out mode caution . . . . . . . . . . . . . . . . . . 22 Multi-drop mode (9-bit or wake-up). . . . . . . . . 22 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register overview . . . . . . . . . . . . . . . . . . . . . . 22 Condensed register bit formats. . . . . . . . . . . . 24 Register descriptions . . . . . . . . . . . . . . . . . . . 26 Mode registers . . . . . . . . . . . . . . . . . . . . . . . . 26 Mode Register 0 channel A (MR0A) . . . . . . . . 26 Mode Register 1 channel A (MR1A) . . . . . . . . 28 Mode Register 2 channel A (MR2A) . . . . . . . . 29 Mode Register 0 channel B (MR0B) . . . . . . . . 32 Mode Register 1 channel B (MR1B) . . . . . . . . 32 Mode Register 2 channel B (MR2B) . . . . . . . . 32 7.3.2 7.3.2.1 7.3.2.2 7.3.3 7.3.3.1 7.3.3.2 7.3.4 7.3.4.1 7.3.4.2 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.3.13 Clock select registers . . . . . . . . . . . . . . . . . . . Clock Select Register channel A (CSRA). . . . Clock Select Register channel B (CSRB). . . . Command registers . . . . . . . . . . . . . . . . . . . . Command Register channel A (CRA) . . . . . . Command Register channel B (CRB) . . . . . . Status registers . . . . . . . . . . . . . . . . . . . . . . . Status Register channel A (SRA). . . . . . . . . . Status Register channel B (SRB). . . . . . . . . . Output Configuration Control Register (OPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Output Port bits Register (SOPR) . . . . . . Reset Output Port bits Register (ROPR) . . . . Output Port Register (OPR) . . . . . . . . . . . . . . Auxiliary Control Register (ACR) . . . . . . . . . . Input Port Change Register (IPCR) . . . . . . . . Interrupt Status Register (ISR). . . . . . . . . . . . Interrupt Mask Register (IMR) . . . . . . . . . . . . Interrupt Vector Register (IVR; 68xxx mode) or General Purpose register (GP; 80xxx mode) . . . . . . . . . . . . . . . . . . . . . Counter/timer registers. . . . . . . . . . . . . . . . . . Output port notes . . . . . . . . . . . . . . . . . . . . . . The CTS, RTS, CTS enable Tx signals . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . Test information. . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 34 35 35 36 37 37 39 39 41 42 43 44 45 45 47
7.3.14 7.4 7.5 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19
48 48 49 49 50 51 54 58 64 65 68 68 68 68 69 70 71 72 72 72 72 72 72 73
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 December 2007 Document identifier: SC28L92_7

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